[PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Luo Jie]

The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
TLMM pinctrl; without this the pins are left in their default state and
the bus does not function on boards that enable it.

Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with
8mA drive strength and pull-up, and reference it from the mdio1 node
via pinctrl-0/pinctrl-names.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 4fc627b47fe7..a8a89a9c8160 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -241,6 +241,8 @@ mdio1: mdio@90000 {
 			reg = <0x00090000 0x64>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			pinctrl-0 = <&mdio_pins>;
+			pinctrl-names = "default";
 
 			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
 			clock-names = "gcc_mdio_ahb_clk";
@@ -427,6 +429,22 @@ uart1_pins: uart1-state {
 				drive-strength = <8>;
 				bias-pull-down;
 			};
+
+			mdio_pins: mdio-state {
+				mdc-pins {
+					pins = "gpio36";
+					function = "mdc";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+
+				mdio-pins {
+					pins = "gpio37";
+					function = "mdio";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
 		};
 
 		gcc: clock-controller@1800000 {

---
base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
change-id: 20260811-qcom_ipq5018_mdio_pinctrl-f9e609e97c3d

Best regards,
--  
Luo Jie <jie.luo@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Kathiravan Thirumoorthy]

On 8/11/2026 7:06 PM, Luo Jie wrote:
> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
> TLMM pinctrl; without this the pins are left in their default state and
> the bus does not function on boards that enable it.

Should we move the TLMM definitions to the board DTS file rather than 
keeping it in the SoC DTSI?

>
> Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with
> 8mA drive strength and pull-up, and reference it from the mdio1 node
> via pinctrl-0/pinctrl-names.
>
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 4fc627b47fe7..a8a89a9c8160 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -241,6 +241,8 @@ mdio1: mdio@90000 {
>   			reg = <0x00090000 0x64>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> +			pinctrl-0 = <&mdio_pins>;
> +			pinctrl-names = "default";
>   
>   			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
>   			clock-names = "gcc_mdio_ahb_clk";
> @@ -427,6 +429,22 @@ uart1_pins: uart1-state {
>   				drive-strength = <8>;
>   				bias-pull-down;
>   			};
> +
> +			mdio_pins: mdio-state {
> +				mdc-pins {
> +					pins = "gpio36";
> +					function = "mdc";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +
> +				mdio-pins {
> +					pins = "gpio37";
> +					function = "mdio";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +			};
>   		};
>   
>   		gcc: clock-controller@1800000 {
>
> ---
> base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
> change-id: 20260811-qcom_ipq5018_mdio_pinctrl-f9e609e97c3d
>
> Best regards,
> --
> Luo Jie <jie.luo@oss.qualcomm.com>
>
>

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Jie Luo]

On 8/11/2026 10:00 PM, Kathiravan Thirumoorthy wrote:
> 
> On 8/11/2026 7:06 PM, Luo Jie wrote:
>> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
>> TLMM pinctrl; without this the pins are left in their default state and
>> the bus does not function on boards that enable it.
> 
> Should we move the TLMM definitions to the board DTS file rather than
> keeping it in the SoC DTSI?

The MDC/MDIO pin-group definition is SoC-specific. On IPQ5018, only
these two TLMM pins support the MDIO interface—one for MDC and one for
MDIO—with no alternative pin assignments available. Therefore, the
definition can remain in the IPQ5018 pinctrl/SoC DTSI for reuse.

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Kathiravan Thirumoorthy]

On 8/11/2026 8:54 PM, Jie Luo wrote:
>
> On 8/11/2026 10:00 PM, Kathiravan Thirumoorthy wrote:
>> On 8/11/2026 7:06 PM, Luo Jie wrote:
>>> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
>>> TLMM pinctrl; without this the pins are left in their default state and
>>> the bus does not function on boards that enable it.
>> Should we move the TLMM definitions to the board DTS file rather than
>> keeping it in the SoC DTSI?
> The MDC/MDIO pin-group definition is SoC-specific. On IPQ5018, only
> these two TLMM pins support the MDIO interface—one for MDC and one for
> MDIO—with no alternative pin assignments available. Therefore, the
> definition can remain in the IPQ5018 pinctrl/SoC DTSI for reuse.

Thanks, As discussed, please send this change along with its consumer.

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Dmitry Baryshkov]

On Tue, Aug 11, 2026 at 11:24:13PM +0800, Jie Luo wrote:
> 
> 
> On 8/11/2026 10:00 PM, Kathiravan Thirumoorthy wrote:
> > 
> > On 8/11/2026 7:06 PM, Luo Jie wrote:
> >> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
> >> TLMM pinctrl; without this the pins are left in their default state and
> >> the bus does not function on boards that enable it.
> > 
> > Should we move the TLMM definitions to the board DTS file rather than
> > keeping it in the SoC DTSI?
> 
> The MDC/MDIO pin-group definition is SoC-specific. On IPQ5018, only
> these two TLMM pins support the MDIO interface—one for MDC and one for
> MDIO—with no alternative pin assignments available. Therefore, the
> definition can remain in the IPQ5018 pinctrl/SoC DTSI for reuse.

Is it expected that the drive strength is also common to all boards?

-- 
With best wishes
Dmitry

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Jie Luo]

On 8/12/2026 5:44 AM, Dmitry Baryshkov wrote:
> On Tue, Aug 11, 2026 at 11:24:13PM +0800, Jie Luo wrote:
>>
>>
>> On 8/11/2026 10:00 PM, Kathiravan Thirumoorthy wrote:
>>>
>>> On 8/11/2026 7:06 PM, Luo Jie wrote:
>>>> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
>>>> TLMM pinctrl; without this the pins are left in their default state and
>>>> the bus does not function on boards that enable it.
>>>
>>> Should we move the TLMM definitions to the board DTS file rather than
>>> keeping it in the SoC DTSI?
>>
>> The MDC/MDIO pin-group definition is SoC-specific. On IPQ5018, only
>> these two TLMM pins support the MDIO interface—one for MDC and one for
>> MDIO—with no alternative pin assignments available. Therefore, the
>> definition can remain in the IPQ5018 pinctrl/SoC DTSI for reuse.
> 
> Is it expected that the drive strength is also common to all boards?
>

Yes. The MDC/MDIO pin configurations, including the drive strength, are
identical across the IPQ5018 RDP boards.

Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Konrad Dybcio]

On 8/11/26 3:36 PM, Luo Jie wrote:
> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
> TLMM pinctrl; without this the pins are left in their default state and
> the bus does not function on boards that enable it.
> 
> Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with
> 8mA drive strength and pull-up, and reference it from the mdio1 node
> via pinctrl-0/pinctrl-names.

This paragraph is a bit heavy on repeating the diff contents (could be
just "Add the missing states and reference them." instead), but overall
this looks good

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad