Re: [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example

[Jon Hunter <jonathanh@nvidia.com>]

On 22/06/2026 07:54, Ashish Mhetre wrote:
> The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
> interrupt documentation, but the binding example describes it as
> level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
> that it does not propagate the wrong trigger type.
> 
> Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
> Reported-by: Nicolin Chen <nicolinc@nvidia.com>
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
>   .../devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml        | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> index 3f5006a59805..76ef34fe5c72 100644
> --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> @@ -38,5 +38,5 @@ examples:
>       cmdqv@5200000 {
>               compatible = "nvidia,tegra264-cmdqv";
>               reg = <0x5200000 0x830000>;
> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
>       };

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon

-- 
nvpublic