From: Jon Hunter <jonathanh@nvidia.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
thierry.reding@kernel.org, nicolinc@nvidia.com
Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264
Date: Wed, 8 Jul 2026 14:32:44 +0100 [thread overview]
Message-ID: <86b1d2e4-e45c-43b3-a0f7-0aaa744d6f36@nvidia.com> (raw)
In-Reply-To: <20260622065410.2780215-2-amhetre@nvidia.com>
On 22/06/2026 07:54, Ashish Mhetre wrote:
> The CMDQV interrupts on Tegra264 are described as level-triggered, but
> per the hardware interrupt documentation these interrupts are actually
> edge-triggered.
>
> Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH
> to IRQ_TYPE_EDGE_RISING.
>
> Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV")
> Reported-by: Nicolin Chen <nicolinc@nvidia.com>
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 2d8e7e37830f..ff9c0476e924 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3393,7 +3393,7 @@ smmu1: iommu@5000000 {
> cmdqv1: cmdqv@5200000 {
> compatible = "nvidia,tegra264-cmdqv";
> reg = <0x00 0x5200000 0x0 0x830000>;
> - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
> status = "disabled";
> };
>
> @@ -3413,7 +3413,7 @@ smmu2: iommu@6000000 {
> cmdqv2: cmdqv@6200000 {
> compatible = "nvidia,tegra264-cmdqv";
> reg = <0x00 0x6200000 0x0 0x830000>;
> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
> status = "disabled";
> };
>
> @@ -3486,7 +3486,7 @@ smmu0: iommu@a000000 {
> cmdqv0: cmdqv@a200000 {
> compatible = "nvidia,tegra264-cmdqv";
> reg = <0x00 0xa200000 0x0 0x830000>;
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
> status = "disabled";
> };
>
> @@ -3506,7 +3506,7 @@ smmu4: iommu@b000000 {
> cmdqv4: cmdqv@b200000 {
> compatible = "nvidia,tegra264-cmdqv";
> reg = <0x00 0xb200000 0x0 0x830000>;
> - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
> status = "disabled";
> };
>
> @@ -3831,7 +3831,7 @@ smmu3: iommu@6000000 {
> cmdqv3: cmdqv@6200000 {
> compatible = "nvidia,tegra264-cmdqv";
> reg = <0x00 0x6200000 0x0 0x830000>;
> - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>;
> status = "disabled";
> };
>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Thanks!
Jon
--
nvpublic
next prev parent reply other threads:[~2026-07-08 13:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 6:54 [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Ashish Mhetre
2026-06-22 6:54 ` [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264 Ashish Mhetre
2026-06-22 20:58 ` Nicolin Chen
2026-07-08 13:32 ` Jon Hunter [this message]
2026-06-22 16:38 ` [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Conor Dooley
2026-06-22 20:52 ` Nicolin Chen
2026-07-08 13:32 ` Jon Hunter
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