Re: [PATCH 3/4] clk: qcom: Add Global Clock controller (GCC) driver for Fillmore

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/8/26 1:39 AM, Aelin Reidel wrote:
> Add support for the global clock controller found on Fillmore (e.g. SM7450)
> based devices.
> 
> Signed-off-by: Aelin Reidel <aelin@mainlining.org>
> ---

[...]

> +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {

This one's a clk_regmap_phy_mux (see other clk drivers for what to
change)

[...]

> +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {

likewise

[...]

> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> +	F(400000, P_BI_TCXO, 12, 1, 4),
> +	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> +	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> +	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> +	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> +	.cmd_rcgr = 0x24014,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_5,
> +	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "gcc_sdcc2_apps_clk_src",
> +		.parent_data = gcc_parent_data_5,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_5),

.flags = CLK_OPS_PARENT_ENABLE,

> +		.ops = &clk_rcg2_ops,

&clk_rcg2_shared_floor_ops

[...]

> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
> +	.cmd_rcgr = 0x8702c,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_10,
> +	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "gcc_ufs_phy_axi_clk_src",
> +		.parent_data = gcc_parent_data_10,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};

please check for .enable_safe_parent or something like that in the downstream
driver - for all RCGs that have it, use clk_rcg2_shared_ops

[...]

> +static struct gdsc pcie_0_gdsc = {
> +	.gdscr = 0x7b004,
> +	.pd = {
> +		.name = "pcie_0_gdsc",
> +	},
> +	.pwrsts = PWRSTS_RET_ON,
> +};
> +
> +static struct gdsc ufs_phy_gdsc = {
> +	.gdscr = 0x87004,
> +	.pd = {
> +		.name = "ufs_phy_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +};
> +
> +static struct gdsc usb30_prim_gdsc = {
> +	.gdscr = 0x49004,
> +	.pd = {
> +		.name = "usb30_prim_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +};

Your downstream DT also has:

HLOS1_VOTE_MMNOC_MMU_TBU_HF[0123]
_SF[01]
_TBU[01]

that all need to be defined and have .flags = VOTABLE

Konrad