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From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Andrew Jones <ajones@ventanamicro.com>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	"Evan Green" <evan@rivosinc.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext()
Date: Mon, 26 Jun 2023 12:19:40 +0100	[thread overview]
Message-ID: <20230626-skydiver-frown-659b982a43ad@wendy> (raw)
In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy>

isa_ext_arr cannot be empty, as some of the extensions within it are
always built into the kernel.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/cpu.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 742bb42e7e86..01f7e5c62997 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -233,10 +233,6 @@ static void print_isa_ext(struct seq_file *f)
 
 	arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
 
-	/* No extension support available */
-	if (arr_sz <= 0)
-		return;
-
 	for (i = 0; i <= arr_sz; i++) {
 		edata = &isa_ext_arr[i];
 		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
-- 
2.40.1


  parent reply	other threads:[~2023-06-26 11:20 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 15:14   ` Andrew Jones
2023-06-26 15:51     ` Conor Dooley
2023-06-26 16:05       ` Andrew Jones
2023-06-26 16:16         ` Conor Dooley
2023-06-27  8:02           ` Sunil V L
2023-06-27  8:51             ` Conor Dooley
2023-06-27  9:20               ` Sunil V L
2023-06-26 11:19 ` Conor Dooley [this message]
2023-06-26 15:19   ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Andrew Jones
2023-06-26 16:08     ` Conor Dooley
2023-06-26 16:29       ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 15:29   ` Andrew Jones
2023-06-26 15:44     ` Andrew Jones
2023-06-26 15:59       ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 15:33   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 15:34   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 15:42   ` Andrew Jones
2023-06-28 17:33   ` Evan Green
2023-06-28 17:43     ` Conor Dooley
2023-06-28 17:50       ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 16:17   ` Andrew Jones
2023-06-27 17:42     ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 16:24   ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 16:25   ` Andrew Jones

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