From: Conor Dooley <conor.dooley@microchip.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>, <palmer@dabbelt.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Evan Green <evan@rivosinc.com>, <linux-riscv@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64
Date: Tue, 27 Jun 2023 09:51:05 +0100 [thread overview]
Message-ID: <20230627-gosling-crouch-635c07ae05b3@wendy> (raw)
In-Reply-To: <ZJqXj7UdegnRP4mI@sunil-laptop>
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On Tue, Jun 27, 2023 at 01:32:23PM +0530, Sunil V L wrote:
> On Mon, Jun 26, 2023 at 05:16:09PM +0100, Conor Dooley wrote:
> > On Mon, Jun 26, 2023 at 06:05:40PM +0200, Andrew Jones wrote:
> > > On Mon, Jun 26, 2023 at 04:51:29PM +0100, Conor Dooley wrote:
> > > > On Mon, Jun 26, 2023 at 05:14:15PM +0200, Andrew Jones wrote:
> > > > > On Mon, Jun 26, 2023 at 12:19:39PM +0100, Conor Dooley wrote:
> > > > One of the few things I know does parsing of /proc/cpuinfo is:
> > > > https://github.com/google/cpu_features/blob/main/src/impl_riscv_linux.c
> > > > and that doesn't seem to care about the mmu, but does rely on
> > > > vendor/uarch ordering.
> > > >
> > > > Makes me wonder, does ACPI break things by leaving out uarch/vendor
> > > > fields, if there is something that expects them to exist? We should
> > > > not intentionally break stuff in /proc/cpuinfo, but can't say I feel any
> > > > sympathy for naively parsing it.
> > >
> > > Yes, it would be nice for ACPI to be consistent. I'm not sure what can be
> > > done about that.
> >
> > Print "unknown", until there's a way of passing the info?
> > Speaking of being an eejit, adding new fields to the file would probably
> > break some really naive parsers & quite frankly that sort of thing can
> > keep the pieces IMO. Ditto if adding more extensions breaks someone that
> > expects _zicbom_zicboz that breaks when _zicbop is slid into the middle.
> Instead of unknown, could you print "risc-v" or "riscv"?
I don't really see how that is better. "riscv" is not the uarch or
vendor. If we don't know, we should either say we don't know or omit the
field IMO.
Cheers,
Conor.
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next prev parent reply other threads:[~2023-06-27 8:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 15:14 ` Andrew Jones
2023-06-26 15:51 ` Conor Dooley
2023-06-26 16:05 ` Andrew Jones
2023-06-26 16:16 ` Conor Dooley
2023-06-27 8:02 ` Sunil V L
2023-06-27 8:51 ` Conor Dooley [this message]
2023-06-27 9:20 ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 15:19 ` Andrew Jones
2023-06-26 16:08 ` Conor Dooley
2023-06-26 16:29 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 15:29 ` Andrew Jones
2023-06-26 15:44 ` Andrew Jones
2023-06-26 15:59 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 15:33 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 15:34 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 15:42 ` Andrew Jones
2023-06-28 17:33 ` Evan Green
2023-06-28 17:43 ` Conor Dooley
2023-06-28 17:50 ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 16:17 ` Andrew Jones
2023-06-27 17:42 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 16:24 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 16:25 ` Andrew Jones
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