* [RFC PATCH 1/8] dt-bindings: nvmem: qfprom: add compatible for MSM8960
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-03 16:38 ` Conor Dooley
2023-07-02 17:50 ` [RFC PATCH 2/8] cpufreq: qcom-nvmem: enable core voltage scaling " Dmitry Baryshkov
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Add the QFPROM compatible for MSM8960.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 6cd4682a167d..d8d0423e8fee 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,ipq8074-qfprom
- qcom,ipq9574-qfprom
- qcom,msm8916-qfprom
+ - qcom,msm8960-qfprom
- qcom,msm8974-qfprom
- qcom,msm8976-qfprom
- qcom,msm8996-qfprom
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [RFC PATCH 1/8] dt-bindings: nvmem: qfprom: add compatible for MSM8960
2023-07-02 17:50 ` [RFC PATCH 1/8] dt-bindings: nvmem: qfprom: add compatible for MSM8960 Dmitry Baryshkov
@ 2023-07-03 16:38 ` Conor Dooley
0 siblings, 0 replies; 17+ messages in thread
From: Conor Dooley @ 2023-07-03 16:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov, linux-arm-msm, devicetree,
linux-pm, linux-clk, Christian Marangi, Stephan Gerhold
[-- Attachment #1: Type: text/plain, Size: 252 bytes --]
On Sun, Jul 02, 2023 at 08:50:38PM +0300, Dmitry Baryshkov wrote:
> Add the QFPROM compatible for MSM8960.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [RFC PATCH 2/8] cpufreq: qcom-nvmem: enable core voltage scaling for MSM8960
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 1/8] dt-bindings: nvmem: qfprom: add compatible for MSM8960 Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 3/8] cpufreq: qcom-nvmem: provide vmin constraint for early Kraits Dmitry Baryshkov
` (5 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Reuse APQ8064 config for MSM8960 to enable core voltage scaling.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 422fd8ca8a00..113f35668048 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -410,7 +410,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
{ .compatible = "qcom,apq8064", .data = &match_data_apq8064 },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
- { .compatible = "qcom,msm8960", .data = &match_data_krait },
+ { .compatible = "qcom,msm8960", .data = &match_data_apq8064 },
{},
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [RFC PATCH 3/8] cpufreq: qcom-nvmem: provide vmin constraint for early Kraits
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 1/8] dt-bindings: nvmem: qfprom: add compatible for MSM8960 Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 2/8] cpufreq: qcom-nvmem: enable core voltage scaling " Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-03 11:38 ` Konrad Dybcio
2023-07-02 17:50 ` [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators Dmitry Baryshkov
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Early Krait CPUs required that core voltage was not below 1.15 V.
Implement this requirement by adding separate config_regulators
callback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 67 +++++++++++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 113f35668048..9312c8ab62a8 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -30,6 +30,8 @@
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>
+#include <asm/cputype.h>
+
#include <dt-bindings/arm/qcom,ids.h>
struct qcom_cpufreq_drv;
@@ -257,6 +259,66 @@ static const struct qcom_cpufreq_match_data match_data_apq8064 = {
.regulator_names = apq8064_regulator_names,
};
+static const int krait_needs_vmin(void)
+{
+ switch (read_cpuid_id()) {
+ case 0x511F04D0: /* KR28M2A20 */
+ case 0x511F04D1: /* KR28M2A21 */
+ case 0x510F06F0: /* KR28M4A10 */
+ return 1;
+ default:
+ return 0;
+ };
+}
+
+#define KRAIT_VMIN 1150000
+#define KRAIT_VMIN_MAX (KRAIT_VMIN + 25000)
+static int krait_config_regulator_vmin(struct device *dev,
+ struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp,
+ struct regulator **regulators, unsigned int count)
+{
+ struct regulator *reg = regulators[0];
+ struct dev_pm_opp_supply supply;
+ int ret;
+
+ /* This function only supports single regulator per device */
+ if (WARN_ON(count > 1)) {
+ dev_err(dev, "multiple regulators are not supported\n");
+ return -EINVAL;
+ }
+
+ if (IS_ERR(reg)) {
+ dev_dbg(dev, "%s: regulator not available: %ld\n", __func__,
+ PTR_ERR(reg));
+ return 0;
+ }
+
+ ret = dev_pm_opp_get_supplies(new_opp, &supply);
+ if (WARN_ON(ret))
+ return ret;
+
+ if (supply.u_volt_min < KRAIT_VMIN) {
+ supply.u_volt_min = KRAIT_VMIN;
+ supply.u_volt = KRAIT_VMIN;
+ supply.u_volt_max = KRAIT_VMIN_MAX;
+ }
+
+ dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+ supply.u_volt_min, supply.u_volt, supply.u_volt_max);
+
+ ret = regulator_set_voltage_triplet(reg,
+ supply.u_volt_min,
+ supply.u_volt,
+ supply.u_volt_max);
+ if (ret)
+ dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
+ __func__, supply.u_volt_min, supply.u_volt,
+ supply.u_volt_max, ret);
+
+ return ret;
+}
+
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -344,8 +406,11 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
config.virt_devs = NULL;
}
- if (drv->data->regulator_names)
+ if (drv->data->regulator_names) {
config.regulator_names = drv->data->regulator_names;
+ if (krait_needs_vmin())
+ config.config_regulators = krait_config_regulator_vmin;
+ }
if (config.supported_hw ||
config.genpd_names ||
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [RFC PATCH 3/8] cpufreq: qcom-nvmem: provide vmin constraint for early Kraits
2023-07-02 17:50 ` [RFC PATCH 3/8] cpufreq: qcom-nvmem: provide vmin constraint for early Kraits Dmitry Baryshkov
@ 2023-07-03 11:38 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2023-07-03 11:38 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On 2.07.2023 19:50, Dmitry Baryshkov wrote:
> Early Krait CPUs required that core voltage was not below 1.15 V.
> Implement this requirement by adding separate config_regulators
> callback.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
"early krait" as in msm8960, or "early krait" as in "pre-production"?
Konrad
> drivers/cpufreq/qcom-cpufreq-nvmem.c | 67 +++++++++++++++++++++++++++-
> 1 file changed, 66 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 113f35668048..9312c8ab62a8 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -30,6 +30,8 @@
> #include <linux/slab.h>
> #include <linux/soc/qcom/smem.h>
>
> +#include <asm/cputype.h>
> +
> #include <dt-bindings/arm/qcom,ids.h>
>
> struct qcom_cpufreq_drv;
> @@ -257,6 +259,66 @@ static const struct qcom_cpufreq_match_data match_data_apq8064 = {
> .regulator_names = apq8064_regulator_names,
> };
>
> +static const int krait_needs_vmin(void)
> +{
> + switch (read_cpuid_id()) {
> + case 0x511F04D0: /* KR28M2A20 */
> + case 0x511F04D1: /* KR28M2A21 */
> + case 0x510F06F0: /* KR28M4A10 */
> + return 1;
> + default:
> + return 0;
> + };
> +}
> +
> +#define KRAIT_VMIN 1150000
> +#define KRAIT_VMIN_MAX (KRAIT_VMIN + 25000)
> +static int krait_config_regulator_vmin(struct device *dev,
> + struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp,
> + struct regulator **regulators, unsigned int count)
> +{
> + struct regulator *reg = regulators[0];
> + struct dev_pm_opp_supply supply;
> + int ret;
> +
> + /* This function only supports single regulator per device */
> + if (WARN_ON(count > 1)) {
> + dev_err(dev, "multiple regulators are not supported\n");
> + return -EINVAL;
> + }
> +
> + if (IS_ERR(reg)) {
> + dev_dbg(dev, "%s: regulator not available: %ld\n", __func__,
> + PTR_ERR(reg));
> + return 0;
> + }
> +
> + ret = dev_pm_opp_get_supplies(new_opp, &supply);
> + if (WARN_ON(ret))
> + return ret;
> +
> + if (supply.u_volt_min < KRAIT_VMIN) {
> + supply.u_volt_min = KRAIT_VMIN;
> + supply.u_volt = KRAIT_VMIN;
> + supply.u_volt_max = KRAIT_VMIN_MAX;
> + }
> +
> + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
> + supply.u_volt_min, supply.u_volt, supply.u_volt_max);
> +
> + ret = regulator_set_voltage_triplet(reg,
> + supply.u_volt_min,
> + supply.u_volt,
> + supply.u_volt_max);
> + if (ret)
> + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
> + __func__, supply.u_volt_min, supply.u_volt,
> + supply.u_volt_max, ret);
> +
> + return ret;
> +}
> +
> +
> static int qcom_cpufreq_probe(struct platform_device *pdev)
> {
> struct qcom_cpufreq_drv *drv;
> @@ -344,8 +406,11 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
> config.virt_devs = NULL;
> }
>
> - if (drv->data->regulator_names)
> + if (drv->data->regulator_names) {
> config.regulator_names = drv->data->regulator_names;
> + if (krait_needs_vmin())
> + config.config_regulators = krait_config_regulator_vmin;
> + }
>
> if (config.supported_hw ||
> config.genpd_names ||
^ permalink raw reply [flat|nested] 17+ messages in thread
* [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
` (2 preceding siblings ...)
2023-07-02 17:50 ` [RFC PATCH 3/8] cpufreq: qcom-nvmem: provide vmin constraint for early Kraits Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-04 13:03 ` Konrad Dybcio
2023-07-02 17:50 ` [RFC PATCH 5/8] ARM: dts: qcom: msm8960-samsung-expressatt: " Dmitry Baryshkov
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
index 414881d34c60..cba0d1e460a1 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
@@ -131,7 +131,7 @@ pm8921_s2: s2 {
};
pm8921_s3: s3 {
- regulator-min-microvolt = <500000>;
+ regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
bias-pull-down;
@@ -287,7 +287,7 @@ pm8921_l23: l23 {
};
pm8921_l24: l24 {
- regulator-min-microvolt = <750000>;
+ regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
bias-pull-down;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators
2023-07-02 17:50 ` [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators Dmitry Baryshkov
@ 2023-07-04 13:03 ` Konrad Dybcio
2023-07-04 13:34 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Konrad Dybcio @ 2023-07-04 13:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On 2.07.2023 19:50, Dmitry Baryshkov wrote:
> Add additional constraints to the CPUfreq-related regulators, it is
> better be safe than sorry there.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I'm squinting quite hard at
https://github.com/LineageOS/sony-kernel-msm8960/blob/jb-dev/arch/arm/mach-msm/acpuclock-8960.c
but I can't figure out where these min values came from
Konrad
> arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> index 414881d34c60..cba0d1e460a1 100644
> --- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> @@ -131,7 +131,7 @@ pm8921_s2: s2 {
> };
>
> pm8921_s3: s3 {
> - regulator-min-microvolt = <500000>;
> + regulator-min-microvolt = <950000>;
> regulator-max-microvolt = <1150000>;
> qcom,switch-mode-frequency = <4800000>;
> bias-pull-down;
> @@ -287,7 +287,7 @@ pm8921_l23: l23 {
> };
>
> pm8921_l24: l24 {
> - regulator-min-microvolt = <750000>;
> + regulator-min-microvolt = <1050000>;
> regulator-max-microvolt = <1150000>;
> bias-pull-down;
> };
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators
2023-07-04 13:03 ` Konrad Dybcio
@ 2023-07-04 13:34 ` Dmitry Baryshkov
2023-07-04 13:50 ` Konrad Dybcio
0 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 13:34 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Ilia Lin, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Michael Turquette, Rafael J. Wysocki, Georgi Djakov,
linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On Tue, 4 Jul 2023 at 16:03, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 2.07.2023 19:50, Dmitry Baryshkov wrote:
> > Add additional constraints to the CPUfreq-related regulators, it is
> > better be safe than sorry there.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> I'm squinting quite hard at
>
> https://github.com/LineageOS/sony-kernel-msm8960/blob/jb-dev/arch/arm/mach-msm/acpuclock-8960.c
>
> but I can't figure out where these min values came from
These should be the minimum values for vdd_min and vdd_dig in
l2_freq_tbl_8960_kraitv2 (v1 is unsupported in mainline).
See below,
>
> Konrad
> > arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> > index 414881d34c60..cba0d1e460a1 100644
> > --- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> > +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
> > @@ -131,7 +131,7 @@ pm8921_s2: s2 {
> > };
> >
> > pm8921_s3: s3 {
> > - regulator-min-microvolt = <500000>;
> > + regulator-min-microvolt = <950000>;
And this is obviously a c&p from 8064. This should be 1050000.
> > regulator-max-microvolt = <1150000>;
> > qcom,switch-mode-frequency = <4800000>;
> > bias-pull-down;
> > @@ -287,7 +287,7 @@ pm8921_l23: l23 {
> > };
> >
> > pm8921_l24: l24 {
> > - regulator-min-microvolt = <750000>;
> > + regulator-min-microvolt = <1050000>;
> > regulator-max-microvolt = <1150000>;
> > bias-pull-down;
> > };
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators
2023-07-04 13:34 ` Dmitry Baryshkov
@ 2023-07-04 13:50 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2023-07-04 13:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Ilia Lin, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Michael Turquette, Rafael J. Wysocki, Georgi Djakov,
linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On 4.07.2023 15:34, Dmitry Baryshkov wrote:
> On Tue, 4 Jul 2023 at 16:03, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 2.07.2023 19:50, Dmitry Baryshkov wrote:
>>> Add additional constraints to the CPUfreq-related regulators, it is
>>> better be safe than sorry there.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> I'm squinting quite hard at
>>
>> https://github.com/LineageOS/sony-kernel-msm8960/blob/jb-dev/arch/arm/mach-msm/acpuclock-8960.c
>>
>> but I can't figure out where these min values came from
>
> These should be the minimum values for vdd_min and vdd_dig in
> l2_freq_tbl_8960_kraitv2 (v1 is unsupported in mainline).
> See below,
>
>>
>> Konrad
>>> arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
>>> index 414881d34c60..cba0d1e460a1 100644
>>> --- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
>>> +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
>>> @@ -131,7 +131,7 @@ pm8921_s2: s2 {
>>> };
>>>
>>> pm8921_s3: s3 {
>>> - regulator-min-microvolt = <500000>;
>>> + regulator-min-microvolt = <950000>;
>
> And this is obviously a c&p from 8064. This should be 1050000.
Okay, please remember to fix all other boards from this patchset too.
Konrad
>
>>> regulator-max-microvolt = <1150000>;
>>> qcom,switch-mode-frequency = <4800000>;
>>> bias-pull-down;
>>> @@ -287,7 +287,7 @@ pm8921_l23: l23 {
>>> };
>>>
>>> pm8921_l24: l24 {
>>> - regulator-min-microvolt = <750000>;
>>> + regulator-min-microvolt = <1050000>;
>>> regulator-max-microvolt = <1150000>;
>>> bias-pull-down;
>>> };
>
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [RFC PATCH 5/8] ARM: dts: qcom: msm8960-samsung-expressatt: constraint cpufreq regulators
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
` (3 preceding siblings ...)
2023-07-02 17:50 ` [RFC PATCH 4/8] ARM: dts: qcom: msm8960-cdp: constraint cpufreq regulators Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 6/8] ARM: dts: qcom: msm8960: add Krait clock controller Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
index 2e7d98e132be..6bc02bf25120 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
@@ -116,7 +116,7 @@ pm8921_s2: s2 {
};
pm8921_s3: s3 {
- regulator-min-microvolt = <500000>;
+ regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
bias-pull-down;
@@ -272,7 +272,7 @@ pm8921_l23: l23 {
};
pm8921_l24: l24 {
- regulator-min-microvolt = <750000>;
+ regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
bias-pull-down;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [RFC PATCH 6/8] ARM: dts: qcom: msm8960: add Krait clock controller
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
` (4 preceding siblings ...)
2023-07-02 17:50 ` [RFC PATCH 5/8] ARM: dts: qcom: msm8960-samsung-expressatt: " Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 7/8] ARM: dts: qcom: msm8960: add L2 cache scaling Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Add device node for the clock controller for the CPU cores and L2
clocks. It will be further used by the L2 and by the CPUfreq nodes.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index ba82b6ab899e..65065276c885 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -81,6 +81,24 @@ sleep_clk: sleep_clk {
};
};
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <&gcc PLL9>, /* hfpll0 */
+ <&gcc PLL10>, /* hfpll1 */
+ <&gcc PLL12>, /* hfpll_l2 */
+ <&acc0>,
+ <&acc1>,
+ <&l2cc>;
+ clock-names = "hfpll0",
+ "hfpll1",
+ "hfpll_l2",
+ "acpu0_aux",
+ "acpu1_aux",
+ "acpu_l2_aux";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [RFC PATCH 7/8] ARM: dts: qcom: msm8960: add L2 cache scaling
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
` (5 preceding siblings ...)
2023-07-02 17:50 ` [RFC PATCH 6/8] ARM: dts: qcom: msm8960: add Krait clock controller Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-02 17:50 ` [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Populate L2 cache node with clock, supplies and OPP information to
facilitate scaling L2 frequency.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 5 +
.../qcom/qcom-msm8960-samsung-expressatt.dts | 5 +
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 124 +++++++++++++++++-
3 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
index cba0d1e460a1..2f73f058d855 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts
@@ -336,6 +336,11 @@ pm8921_ncp: ncp {
};
};
+&L2 {
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+};
+
/* eMMC */
&sdcc1 {
status = "okay";
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
index 6bc02bf25120..7132255c7003 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
@@ -321,6 +321,11 @@ pm8921_ncp: ncp {
};
};
+&L2 {
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+};
+
&usb_hs1_phy {
v3p3-supply = <&pm8921_l3>;
v1p8-supply = <&pm8921_l4>;
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 65065276c885..48b3962dd4fb 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,krait-cc.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
@@ -41,9 +42,130 @@ cpu@1 {
};
L2: l2-cache {
- compatible = "cache";
+ compatible = "qcom,krait-l2-cache", "cache";
cache-level = <2>;
cache-unified;
+ clocks = <&kraitcc KRAIT_L2>;
+ #interconnect-cells = <1>;
+ operating-points-v2 = <&l2_opp_table>;
+
+ l2_opp_table: opp-table-l2 {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-486000000 {
+ opp-hz = /bits/ 64 <486000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-594000000 {
+ opp-hz = /bits/ 64 <594000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <1050000 1050000 1050000>,
+ <1050000 1050000 1050000>;
+ };
+
+ opp-756000000 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-972000000 {
+ opp-hz = /bits/ 64 <972000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1026000000 {
+ opp-hz = /bits/ 64 <1026000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1134000000 {
+ opp-hz = /bits/ 64 <1134000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1188000000 {
+ opp-hz = /bits/ 64 <1188000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1242000000 {
+ opp-hz = /bits/ 64 <1242000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-microvolt = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>;
+ };
+ };
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support
2023-07-02 17:50 [RFC PATCH 0/8] ARM: qcom: msm8960: support CPU frequency scaling Dmitry Baryshkov
` (6 preceding siblings ...)
2023-07-02 17:50 ` [RFC PATCH 7/8] ARM: dts: qcom: msm8960: add L2 cache scaling Dmitry Baryshkov
@ 2023-07-02 17:50 ` Dmitry Baryshkov
2023-07-04 13:05 ` Konrad Dybcio
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-02 17:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
Declare CPU frequency-scaling properties. Each CPU has its own clock,
how all CPUs have the same OPP table. Voltage scaling is not (yet)
enabled with this patch. It will be enabled later.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 147 +++++++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 48b3962dd4fb..995ea32f8d66 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/soc/qcom,krait-l2-cache.h>
/ {
#address-cells = <1>;
@@ -29,6 +30,13 @@ cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ clocks = <&kraitcc KRAIT_CPU_0>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ vdd-core-supply = <&saw0_vreg>;
+ interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
cpu@1 {
@@ -39,6 +47,13 @@ cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ clocks = <&kraitcc KRAIT_CPU_0>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ vdd-core-supply = <&saw1_vreg>;
+ interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
L2: l2-cache {
@@ -169,6 +184,127 @@ opp-1350000000 {
};
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-krait-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-peak-kBps = <384000>;
+ opp-microvolt-speed0-pvs0 = <950000 950000 950000>;
+ opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
+ opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
+ opp-supported-hw = <0x1>;
+ /*
+ * higher latency as it requires switching between
+ * clock sources
+ */
+ clock-latency-ns = <244144>;
+ };
+
+ opp-486000000 {
+ opp-hz = /bits/ 64 <486000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <975000 975000 975000>;
+ opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
+ opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-594000000 {
+ opp-hz = /bits/ 64 <594000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <1000000 1000000 1000000>;
+ opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
+ opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <1025000 1025000 1025000>;
+ opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
+ opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <1075000 1075000 1075000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
+ opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <1100000 1100000 1100000>;
+ opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
+ opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1026000000 {
+ opp-hz = /bits/ 64 <1026000000>;
+ opp-peak-kBps = <702000>;
+ opp-microvolt-speed0-pvs0 = <1125000 1125000 1125000>;
+ opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1134000000 {
+ opp-hz = /bits/ 64 <1134000000>;
+ opp-peak-kBps = <1350000>;
+ opp-microvolt-speed0-pvs0 = <1175000 1175000 1175000>;
+ opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
+ opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1242000000 {
+ opp-hz = /bits/ 64 <1242000000>;
+ opp-peak-kBps = <1350000>;
+ opp-microvolt-speed0-pvs0 = <1200000 1200000 1200000>;
+ opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
+ opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-peak-kBps = <1350000>;
+ opp-microvolt-speed0-pvs0 = <1225000 1225000 1225000>;
+ opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
+ opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1458000000 {
+ opp-hz = /bits/ 64 <1458000000>;
+ opp-peak-kBps = <1350000>;
+ opp-microvolt-speed0-pvs0 = <1237500 1237500 1237500>;
+ opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
+ opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-peak-kBps = <1350000>;
+ opp-microvolt-speed0-pvs0 = <1250000 1250000 1250000>;
+ opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
+ opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x0>;
@@ -266,6 +402,17 @@ msmgpio: pinctrl@800000 {
reg = <0x800000 0x4000>;
};
+ qfprom: qfprom@700000 {
+ compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
+ reg = <0x00700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0x0c0 0x4>;
+ };
+ };
+
gcc: clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
#clock-cells = <1>;
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support
2023-07-02 17:50 ` [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
@ 2023-07-04 13:05 ` Konrad Dybcio
2023-07-04 13:44 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Konrad Dybcio @ 2023-07-04 13:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, Georgi Djakov
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On 2.07.2023 19:50, Dmitry Baryshkov wrote:
Subject: wrong soc
> Declare CPU frequency-scaling properties. Each CPU has its own clock,
> how all CPUs have the same OPP table. Voltage scaling is not (yet)
> enabled with this patch. It will be enabled later.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---Same concern as patch 4, can't see where these values came from.
Konrad
> arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 147 +++++++++++++++++++++++
> 1 file changed, 147 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> index 48b3962dd4fb..995ea32f8d66 100644
> --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/qcom,lcc-msm8960.h>
> #include <dt-bindings/mfd/qcom-rpm.h>
> #include <dt-bindings/soc/qcom,gsbi.h>
> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
>
> / {
> #address-cells = <1>;
> @@ -29,6 +30,13 @@ cpu@0 {
> next-level-cache = <&L2>;
> qcom,acc = <&acc0>;
> qcom,saw = <&saw0>;
> + clocks = <&kraitcc KRAIT_CPU_0>;
> + clock-names = "cpu";
> + clock-latency = <100000>;
> + vdd-core-supply = <&saw0_vreg>;
> + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> + operating-points-v2 = <&cpu_opp_table>;
> + #cooling-cells = <2>;
> };
>
> cpu@1 {
> @@ -39,6 +47,13 @@ cpu@1 {
> next-level-cache = <&L2>;
> qcom,acc = <&acc1>;
> qcom,saw = <&saw1>;
> + clocks = <&kraitcc KRAIT_CPU_0>;
> + clock-names = "cpu";
> + clock-latency = <100000>;
> + vdd-core-supply = <&saw1_vreg>;
> + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> + operating-points-v2 = <&cpu_opp_table>;
> + #cooling-cells = <2>;
> };
>
> L2: l2-cache {
> @@ -169,6 +184,127 @@ opp-1350000000 {
> };
> };
>
> + cpu_opp_table: opp-table-cpu {
> + compatible = "operating-points-v2-krait-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> +
> + /*
> + * Voltage thresholds are <target min max>
> + */
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-peak-kBps = <384000>;
> + opp-microvolt-speed0-pvs0 = <950000 950000 950000>;
> + opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
> + opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
> + opp-supported-hw = <0x1>;
> + /*
> + * higher latency as it requires switching between
> + * clock sources
> + */
> + clock-latency-ns = <244144>;
> + };
> +
> + opp-486000000 {
> + opp-hz = /bits/ 64 <486000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <975000 975000 975000>;
> + opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
> + opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-594000000 {
> + opp-hz = /bits/ 64 <594000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <1000000 1000000 1000000>;
> + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
> + opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-702000000 {
> + opp-hz = /bits/ 64 <702000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <1025000 1025000 1025000>;
> + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
> + opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <1075000 1075000 1075000>;
> + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
> + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-918000000 {
> + opp-hz = /bits/ 64 <918000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <1100000 1100000 1100000>;
> + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
> + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1026000000 {
> + opp-hz = /bits/ 64 <1026000000>;
> + opp-peak-kBps = <702000>;
> + opp-microvolt-speed0-pvs0 = <1125000 1125000 1125000>;
> + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
> + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1134000000 {
> + opp-hz = /bits/ 64 <1134000000>;
> + opp-peak-kBps = <1350000>;
> + opp-microvolt-speed0-pvs0 = <1175000 1175000 1175000>;
> + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
> + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1242000000 {
> + opp-hz = /bits/ 64 <1242000000>;
> + opp-peak-kBps = <1350000>;
> + opp-microvolt-speed0-pvs0 = <1200000 1200000 1200000>;
> + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
> + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1350000000 {
> + opp-hz = /bits/ 64 <1350000000>;
> + opp-peak-kBps = <1350000>;
> + opp-microvolt-speed0-pvs0 = <1225000 1225000 1225000>;
> + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
> + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1458000000 {
> + opp-hz = /bits/ 64 <1458000000>;
> + opp-peak-kBps = <1350000>;
> + opp-microvolt-speed0-pvs0 = <1237500 1237500 1237500>;
> + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
> + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
> + opp-supported-hw = <0x1>;
> + };
> +
> + opp-1512000000 {
> + opp-hz = /bits/ 64 <1512000000>;
> + opp-peak-kBps = <1350000>;
> + opp-microvolt-speed0-pvs0 = <1250000 1250000 1250000>;
> + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
> + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
> + opp-supported-hw = <0x1>;
> + };
> + };
> +
> memory {
> device_type = "memory";
> reg = <0x0 0x0>;
> @@ -266,6 +402,17 @@ msmgpio: pinctrl@800000 {
> reg = <0x800000 0x4000>;
> };
>
> + qfprom: qfprom@700000 {
> + compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
> + reg = <0x00700000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + speedbin_efuse: speedbin@c0 {
> + reg = <0x0c0 0x4>;
> + };
> + };
> +
> gcc: clock-controller@900000 {
> compatible = "qcom,gcc-msm8960";
> #clock-cells = <1>;
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support
2023-07-04 13:05 ` Konrad Dybcio
@ 2023-07-04 13:44 ` Dmitry Baryshkov
2023-07-04 13:49 ` Konrad Dybcio
0 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 13:44 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Ilia Lin, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Michael Turquette, Rafael J. Wysocki, Georgi Djakov,
linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On Tue, 4 Jul 2023 at 16:05, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 2.07.2023 19:50, Dmitry Baryshkov wrote:
>
> Subject: wrong soc
>
> > Declare CPU frequency-scaling properties. Each CPU has its own clock,
> > how all CPUs have the same OPP table. Voltage scaling is not (yet)
> > enabled with this patch. It will be enabled later.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---Same concern as patch 4, can't see where these values came from.
Explained below.
Please use https://android.googlesource.com/kernel/msm/+/android-msm-hammerhead-3.4-marshmallow-mr2/arch/arm/mach-msm/acpuclock-8960.c
as a reference.
>
> Konrad
> > arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 147 +++++++++++++++++++++++
> > 1 file changed, 147 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > index 48b3962dd4fb..995ea32f8d66 100644
> > --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
> > @@ -8,6 +8,7 @@
> > #include <dt-bindings/clock/qcom,lcc-msm8960.h>
> > #include <dt-bindings/mfd/qcom-rpm.h>
> > #include <dt-bindings/soc/qcom,gsbi.h>
> > +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
> >
> > / {
> > #address-cells = <1>;
> > @@ -29,6 +30,13 @@ cpu@0 {
> > next-level-cache = <&L2>;
> > qcom,acc = <&acc0>;
> > qcom,saw = <&saw0>;
> > + clocks = <&kraitcc KRAIT_CPU_0>;
> > + clock-names = "cpu";
> > + clock-latency = <100000>;
> > + vdd-core-supply = <&saw0_vreg>;
> > + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> > + operating-points-v2 = <&cpu_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > cpu@1 {
> > @@ -39,6 +47,13 @@ cpu@1 {
> > next-level-cache = <&L2>;
> > qcom,acc = <&acc1>;
> > qcom,saw = <&saw1>;
> > + clocks = <&kraitcc KRAIT_CPU_0>;
> > + clock-names = "cpu";
> > + clock-latency = <100000>;
> > + vdd-core-supply = <&saw1_vreg>;
> > + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> > + operating-points-v2 = <&cpu_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > L2: l2-cache {
> > @@ -169,6 +184,127 @@ opp-1350000000 {
> > };
> > };
> >
> > + cpu_opp_table: opp-table-cpu {
> > + compatible = "operating-points-v2-krait-cpu";
> > + nvmem-cells = <&speedbin_efuse>;
> > +
> > + /*
> > + * Voltage thresholds are <target min max>
> > + */
> > + opp-384000000 {
> > + opp-hz = /bits/ 64 <384000000>;
> > + opp-peak-kBps = <384000>;
> > + opp-microvolt-speed0-pvs0 = <950000 950000 950000>;
acpu_freq_tbl_slow, the voltage column.
For the PVS_SLOW the pvs_tables doesn't list turbo boost, so all three
voltages are the same.
> > + opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
This comes from acpu_freq_tbl_nom. The voltage from the table becomes
the middle value (min).
For PVS_NOM the pvs_tables has the turbo value (25000), which
acpuclock-krait applied by default, this becomes the first (target)
value.
For maximum I added another 25 mV to account for this exact value not
being supported by the core (SAW) regulator.
> > + opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
> > + opp-supported-hw = <0x1>;
> > + /*
> > + * higher latency as it requires switching between
> > + * clock sources
> > + */
> > + clock-latency-ns = <244144>;
> > + };
> > +
> > + opp-486000000 {
> > + opp-hz = /bits/ 64 <486000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <975000 975000 975000>;
> > + opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
> > + opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-594000000 {
> > + opp-hz = /bits/ 64 <594000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1000000 1000000 1000000>;
> > + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
> > + opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-702000000 {
> > + opp-hz = /bits/ 64 <702000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1025000 1025000 1025000>;
> > + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
> > + opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-810000000 {
> > + opp-hz = /bits/ 64 <810000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1075000 1075000 1075000>;
> > + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
> > + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-918000000 {
> > + opp-hz = /bits/ 64 <918000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1100000 1100000 1100000>;
> > + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
> > + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1026000000 {
> > + opp-hz = /bits/ 64 <1026000000>;
> > + opp-peak-kBps = <702000>;
> > + opp-microvolt-speed0-pvs0 = <1125000 1125000 1125000>;
> > + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
> > + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1134000000 {
> > + opp-hz = /bits/ 64 <1134000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1175000 1175000 1175000>;
> > + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
> > + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1242000000 {
> > + opp-hz = /bits/ 64 <1242000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1200000 1200000 1200000>;
> > + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
> > + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1350000000 {
> > + opp-hz = /bits/ 64 <1350000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1225000 1225000 1225000>;
> > + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
> > + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1458000000 {
> > + opp-hz = /bits/ 64 <1458000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1237500 1237500 1237500>;
> > + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
> > + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
> > + opp-supported-hw = <0x1>;
> > + };
> > +
> > + opp-1512000000 {
> > + opp-hz = /bits/ 64 <1512000000>;
> > + opp-peak-kBps = <1350000>;
> > + opp-microvolt-speed0-pvs0 = <1250000 1250000 1250000>;
> > + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
> > + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
> > + opp-supported-hw = <0x1>;
> > + };
> > + };
> > +
> > memory {
> > device_type = "memory";
> > reg = <0x0 0x0>;
> > @@ -266,6 +402,17 @@ msmgpio: pinctrl@800000 {
> > reg = <0x800000 0x4000>;
> > };
> >
> > + qfprom: qfprom@700000 {
> > + compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
> > + reg = <0x00700000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > + speedbin_efuse: speedbin@c0 {
> > + reg = <0x0c0 0x4>;
> > + };
> > + };
> > +
> > gcc: clock-controller@900000 {
> > compatible = "qcom,gcc-msm8960";
> > #clock-cells = <1>;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [RFC PATCH 8/8] ARM: dts: qcom: apq8064: add simple CPUFreq support
2023-07-04 13:44 ` Dmitry Baryshkov
@ 2023-07-04 13:49 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2023-07-04 13:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Ilia Lin, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Michael Turquette, Rafael J. Wysocki, Georgi Djakov,
linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi,
Stephan Gerhold
On 4.07.2023 15:44, Dmitry Baryshkov wrote:
> On Tue, 4 Jul 2023 at 16:05, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 2.07.2023 19:50, Dmitry Baryshkov wrote:
>>
>> Subject: wrong soc
>>
>>> Declare CPU frequency-scaling properties. Each CPU has its own clock,
>>> how all CPUs have the same OPP table. Voltage scaling is not (yet)
>>> enabled with this patch. It will be enabled later.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---Same concern as patch 4, can't see where these values came from.
>
> Explained below.
>
> Please use https://android.googlesource.com/kernel/msm/+/android-msm-hammerhead-3.4-marshmallow-mr2/arch/arm/mach-msm/acpuclock-8960.c
> as a reference.
>
>>
>> Konrad
>>> arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 147 +++++++++++++++++++++++
>>> 1 file changed, 147 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
>>> index 48b3962dd4fb..995ea32f8d66 100644
>>> --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
>>> +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
>>> @@ -8,6 +8,7 @@
>>> #include <dt-bindings/clock/qcom,lcc-msm8960.h>
>>> #include <dt-bindings/mfd/qcom-rpm.h>
>>> #include <dt-bindings/soc/qcom,gsbi.h>
>>> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
>>>
>>> / {
>>> #address-cells = <1>;
>>> @@ -29,6 +30,13 @@ cpu@0 {
>>> next-level-cache = <&L2>;
>>> qcom,acc = <&acc0>;
>>> qcom,saw = <&saw0>;
>>> + clocks = <&kraitcc KRAIT_CPU_0>;
>>> + clock-names = "cpu";
>>> + clock-latency = <100000>;
>>> + vdd-core-supply = <&saw0_vreg>;
>>> + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> cpu@1 {
>>> @@ -39,6 +47,13 @@ cpu@1 {
>>> next-level-cache = <&L2>;
>>> qcom,acc = <&acc1>;
>>> qcom,saw = <&saw1>;
>>> + clocks = <&kraitcc KRAIT_CPU_0>;
>>> + clock-names = "cpu";
>>> + clock-latency = <100000>;
>>> + vdd-core-supply = <&saw1_vreg>;
>>> + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> L2: l2-cache {
>>> @@ -169,6 +184,127 @@ opp-1350000000 {
>>> };
>>> };
>>>
>>> + cpu_opp_table: opp-table-cpu {
>>> + compatible = "operating-points-v2-krait-cpu";
>>> + nvmem-cells = <&speedbin_efuse>;
>>> +
>>> + /*
>>> + * Voltage thresholds are <target min max>
>>> + */
>>> + opp-384000000 {
>>> + opp-hz = /bits/ 64 <384000000>;
>>> + opp-peak-kBps = <384000>;
>>> + opp-microvolt-speed0-pvs0 = <950000 950000 950000>;
>
> acpu_freq_tbl_slow, the voltage column.
> For the PVS_SLOW the pvs_tables doesn't list turbo boost, so all three
> voltages are the same.
>
>>> + opp-microvolt-speed0-pvs1 = <925000 900000 950000>;
>
> This comes from acpu_freq_tbl_nom. The voltage from the table becomes
> the middle value (min).
> For PVS_NOM the pvs_tables has the turbo value (25000), which
> acpuclock-krait applied by default, this becomes the first (target)
> value.
> For maximum I added another 25 mV to account for this exact value not
> being supported by the core (SAW) regulator.
And PVS3 seems to be correlated with acpu_freq_tbl_fast. Ok.
Makes sense now.
One nit below.
>
>
>>> + opp-microvolt-speed0-pvs3 = <875000 850000 900000>;
>>> + opp-supported-hw = <0x1>;
>>> + /*
>>> + * higher latency as it requires switching between
>>> + * clock sources
>>> + */
>>> + clock-latency-ns = <244144>;
>>> + };
>>> +
>>> + opp-486000000 {
>>> + opp-hz = /bits/ 64 <486000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <975000 975000 975000>;
>>> + opp-microvolt-speed0-pvs1 = <950000 925000 975000>;
>>> + opp-microvolt-speed0-pvs3 = <900000 875000 925000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-594000000 {
>>> + opp-hz = /bits/ 64 <594000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <1000000 1000000 1000000>;
>>> + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>;
>>> + opp-microvolt-speed0-pvs3 = <925000 900000 950000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-702000000 {
>>> + opp-hz = /bits/ 64 <702000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <1025000 1025000 1025000>;
>>> + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>;
>>> + opp-microvolt-speed0-pvs3 = <950000 925000 975000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-810000000 {
>>> + opp-hz = /bits/ 64 <810000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <1075000 1075000 1075000>;
>>> + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>;
>>> + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-918000000 {
>>> + opp-hz = /bits/ 64 <918000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <1100000 1100000 1100000>;
>>> + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>;
>>> + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1026000000 {
>>> + opp-hz = /bits/ 64 <1026000000>;
>>> + opp-peak-kBps = <702000>;
>>> + opp-microvolt-speed0-pvs0 = <1125000 1125000 1125000>;
>>> + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>;
>>> + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1134000000 {
>>> + opp-hz = /bits/ 64 <1134000000>;
>>> + opp-peak-kBps = <1350000>;
>>> + opp-microvolt-speed0-pvs0 = <1175000 1175000 1175000>;
>>> + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>;
>>> + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1242000000 {
>>> + opp-hz = /bits/ 64 <1242000000>;
>>> + opp-peak-kBps = <1350000>;
>>> + opp-microvolt-speed0-pvs0 = <1200000 1200000 1200000>;
>>> + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>;
>>> + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1350000000 {
>>> + opp-hz = /bits/ 64 <1350000000>;
>>> + opp-peak-kBps = <1350000>;
>>> + opp-microvolt-speed0-pvs0 = <1225000 1225000 1225000>;
>>> + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>;
>>> + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1458000000 {
>>> + opp-hz = /bits/ 64 <1458000000>;
>>> + opp-peak-kBps = <1350000>;
>>> + opp-microvolt-speed0-pvs0 = <1237500 1237500 1237500>;
>>> + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>;
>>> + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> +
>>> + opp-1512000000 {
>>> + opp-hz = /bits/ 64 <1512000000>;
>>> + opp-peak-kBps = <1350000>;
>>> + opp-microvolt-speed0-pvs0 = <1250000 1250000 1250000>;
>>> + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>;
>>> + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>;
>>> + opp-supported-hw = <0x1>;
>>> + };
>>> + };
>>> +
>>> memory {
>>> device_type = "memory";
>>> reg = <0x0 0x0>;
>>> @@ -266,6 +402,17 @@ msmgpio: pinctrl@800000 {
>>> reg = <0x800000 0x4000>;
>>> };
>>>
>>> + qfprom: qfprom@700000 {
>>> + compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
>>> + reg = <0x00700000 0x1000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
Please add a newline before the subnode.
Konrad
>>> + speedbin_efuse: speedbin@c0 {
>>> + reg = <0x0c0 0x4>;
>>> + };
>>> + };
>>> +
>>> gcc: clock-controller@900000 {
>>> compatible = "qcom,gcc-msm8960";
>>> #clock-cells = <1>;
>
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread