* [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-12-06 17:09 ` Palmer Dabbelt
2023-11-30 15:19 ` [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties Emil Renner Berthing
` (8 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven, Conor Dooley
This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/Kconfig.errata | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e2c731cfed8c..692de149141f 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200
If you don't know what to do here, say "Y".
+config ERRATA_STARFIVE_JH7100
+ bool "StarFive JH7100 support"
+ depends on ARCH_STARFIVE && NONPORTABLE
+ select DMA_GLOBAL_POOL
+ select RISCV_DMA_NONCOHERENT
+ select RISCV_NONSTANDARD_CACHE_OPS
+ select SIFIVE_CCACHE
+ default n
+ help
+ The StarFive JH7100 was a test chip for the JH7110 and has
+ caches that are non-coherent with respect to peripheral DMAs.
+ It was designed before the Zicbom extension so needs non-standard
+ cache operations through the SiFive cache controller.
+
+ Say "Y" if you want to support the BeagleV Starlight and/or
+ StarFive VisionFive V1 boards.
+
config ERRATA_THEAD
bool "T-HEAD errata"
depends on RISCV_ALTERNATIVE
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata
2023-11-30 15:19 ` [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Emil Renner Berthing
@ 2023-12-06 17:09 ` Palmer Dabbelt
0 siblings, 0 replies; 14+ messages in thread
From: Palmer Dabbelt @ 2023-12-06 17:09 UTC (permalink / raw)
To: emil.renner.berthing
Cc: linux-riscv, devicetree, linux-kernel, Paul Walmsley, kernel,
Conor Dooley, robh+dt, krzysztof.kozlowski+dt, cristian.ciocaltea,
geert, Conor Dooley
On Thu, 30 Nov 2023 07:19:25 PST (-0800), emil.renner.berthing@canonical.com wrote:
> This not really an errata, but since the JH7100 was made before
> the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
> RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> ---
> arch/riscv/Kconfig.errata | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e2c731cfed8c..692de149141f 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200
>
> If you don't know what to do here, say "Y".
>
> +config ERRATA_STARFIVE_JH7100
> + bool "StarFive JH7100 support"
> + depends on ARCH_STARFIVE && NONPORTABLE
> + select DMA_GLOBAL_POOL
> + select RISCV_DMA_NONCOHERENT
> + select RISCV_NONSTANDARD_CACHE_OPS
> + select SIFIVE_CCACHE
> + default n
> + help
> + The StarFive JH7100 was a test chip for the JH7110 and has
> + caches that are non-coherent with respect to peripheral DMAs.
> + It was designed before the Zicbom extension so needs non-standard
> + cache operations through the SiFive cache controller.
> +
> + Say "Y" if you want to support the BeagleV Starlight and/or
> + StarFive VisionFive V1 boards.
> +
> config ERRATA_THEAD
> bool "T-HEAD errata"
> depends on RISCV_ALTERNATIVE
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Thanks for dealing with this. This is mostly DT stuff so I'm fine with
it going via Conor's tree, but LMK if you guys want me to take it.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Emil Renner Berthing
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Geert Uytterhoeven, Paul Walmsley, Palmer Dabbelt,
Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Cristian Ciocaltea
From: Geert Uytterhoeven <geert@linux-m68k.org>
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts-extended" properties
using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index e68cafe7545f..a40a8544b860 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -149,15 +149,15 @@ soc {
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
- &cpu1_intc 11 &cpu1_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller Emil Renner Berthing
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Emil Renner Berthing, Paul Walmsley, Palmer Dabbelt, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
From: Emil Renner Berthing <kernel@esmil.dk>
The StarFive JH7100 SoC has non-coherent device DMAs, so mark the
soc bus as such.
Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index a40a8544b860..7c1009428c1f 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -144,6 +144,7 @@ soc {
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
+ dma-noncoherent;
ranges;
clint: clint@2000000 {
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (2 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Emil Renner Berthing
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 7c1009428c1f..0cafac437746 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -32,6 +32,7 @@ U74_0: cpu@0 {
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@@ -60,6 +61,7 @@ U74_1: cpu@1 {
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@@ -154,6 +156,17 @@ clint: clint@2000000 {
<&cpu1_intc 3>, <&cpu1_intc 7>;
};
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ interrupts = <128>, <130>, <131>, <129>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (3 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes Emil Renner Berthing
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers
expect to be able to allocate coherent memory for DMA descriptors and
such. However on the JH7100 DDR memory appears twice in the physical
memory map, once cached and once uncached:
0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached
0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached
To use this uncached region we create a global DMA memory pool there and
reserve the corresponding area in the cached region.
However the uncached region is fully above the 32bit address limit, so add
a dma-ranges map so the DMA address used for peripherals is still in the
regular cached region below the limit.
Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
.../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..3af88e6970a3 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -39,6 +39,30 @@ led-ack {
label = "ack";
};
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dma-reserved@fa000000 {
+ reg = <0x0 0xfa000000 0x0 0x1000000>;
+ no-map;
+ };
+
+ linux,dma@107a000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10 0x7a000000 0x0 0x1000000>;
+ no-map;
+ linux,dma-default;
+ };
+ };
+
+ soc {
+ dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
+ <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
+ <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
+ };
};
&gpio {
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (4 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Emil Renner Berthing
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
Add device tree nodes for the Synopsis MMC controllers on the
StarFive JH7100 SoC.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 0cafac437746..c216aaecac53 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -178,6 +178,32 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <133>;
};
+ sdio0: mmc@10000000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
+ <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
+ clock-names = "biu", "ciu";
+ interrupts = <4>;
+ data-addr = <0>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ status = "disabled";
+ };
+
+ sdio1: mmc@10010000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
+ <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
+ clock-names = "biu", "ciu";
+ interrupts = <5>;
+ data-addr = <0>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ status = "disabled";
+ };
+
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (5 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-11-30 15:19 ` [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi " Emil Renner Berthing
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
Add pinctrl and MMC device tree nodes for the SD-card on the
BeagleV Starlight and StarFive VisionFive V1 boards.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
.../boot/dts/starfive/jh7100-common.dtsi | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 3af88e6970a3..adcdbbc4f57f 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
+ mmc0 = &sdio0;
serial0 = &uart3;
};
@@ -108,6 +109,43 @@ GPO_I2C2_PAD_SDA_OEN,
};
};
+ sdio0_pins: sdio0-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
+ GPO_ENABLE, GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ sdio-pins {
+ pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
+ GPI_SDIO0_PAD_CARD_DETECT_N)>,
+ <GPIOMUX(53,
+ GPO_SDIO0_PAD_CCMD_OUT,
+ GPO_SDIO0_PAD_CCMD_OEN,
+ GPI_SDIO0_PAD_CCMD_IN)>,
+ <GPIOMUX(49,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT0,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT0,
+ GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
+ <GPIOMUX(50,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT1,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT1,
+ GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
+ <GPIOMUX(51,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT2,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT2,
+ GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
+ <GPIOMUX(52,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT3,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT3,
+ GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -178,6 +216,15 @@ &osc_aud {
clock-frequency = <27000000>;
};
+&sdio0 {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_pins>;
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (6 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Emil Renner Berthing
@ 2023-11-30 15:19 ` Emil Renner Berthing
2023-12-13 15:42 ` (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree Conor Dooley
2023-12-13 15:53 ` Conor Dooley
9 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-11-30 15:19 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea,
Geert Uytterhoeven
Add pinctrl and MMC controller nodes for the Broadcom wifi controller
on the BeagleV Starlight and StarFive VisionFive V1 boards.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
.../boot/dts/starfive/jh7100-common.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index adcdbbc4f57f..42fb61c36068 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -13,6 +13,7 @@
/ {
aliases {
mmc0 = &sdio0;
+ mmc1 = &sdio1;
serial0 = &uart3;
};
@@ -64,6 +65,11 @@ soc {
<0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
<0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
};
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ };
};
&gpio {
@@ -146,6 +152,41 @@ GPO_SDIO0_PAD_CDATA_OEN_BIT3,
};
};
+ sdio1_pins: sdio1-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
+ GPO_ENABLE, GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ sdio-pins {
+ pinmux = <GPIOMUX(29,
+ GPO_SDIO1_PAD_CCMD_OUT,
+ GPO_SDIO1_PAD_CCMD_OEN,
+ GPI_SDIO1_PAD_CCMD_IN)>,
+ <GPIOMUX(36,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT0,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT0,
+ GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
+ <GPIOMUX(30,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT1,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT1,
+ GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
+ <GPIOMUX(34,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT2,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT2,
+ GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
+ <GPIOMUX(31,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT3,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT3,
+ GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -225,6 +266,25 @@ &sdio0 {
status = "okay";
};
+&sdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ cap-power-off-card;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio1_pins>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
--
2.40.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (7 preceding siblings ...)
2023-11-30 15:19 ` [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi " Emil Renner Berthing
@ 2023-12-13 15:42 ` Conor Dooley
2023-12-13 15:51 ` Geert Uytterhoeven
2023-12-13 15:53 ` Conor Dooley
9 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2023-12-13 15:42 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel, Emil Renner Berthing
Cc: conor, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Cristian Ciocaltea, Geert Uytterhoeven
From: Conor Dooley <conor.dooley@microchip.com>
On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> Now that the driver for the SiFive cache controller supports manual
> flushing as non-standard cache operations[1] we can add an errata option
> for the StarFive JH7100 SoC and update the device tree with the cache
> controller, dedicated DMA pool and add MMC nodes for the SD-card and
> wifi.
>
> This series needs the following commit in [1] to work properly:
>
> [...]
Applied to riscv-cache-for-next, thanks!
[1/8] riscv: errata: Add StarFive JH7100 errata
https://git.kernel.org/conor/c/64fc984a8a54
Thanks,
Conor.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
2023-12-13 15:42 ` (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree Conor Dooley
@ 2023-12-13 15:51 ` Geert Uytterhoeven
2023-12-15 19:13 ` Emil Renner Berthing
0 siblings, 1 reply; 14+ messages in thread
From: Geert Uytterhoeven @ 2023-12-13 15:51 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, linux-kernel, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea
Hi Conor,
On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> > Now that the driver for the SiFive cache controller supports manual
> > flushing as non-standard cache operations[1] we can add an errata option
> > for the StarFive JH7100 SoC and update the device tree with the cache
> > controller, dedicated DMA pool and add MMC nodes for the SD-card and
> > wifi.
> >
> > This series needs the following commit in [1] to work properly:
> >
> > [...]
>
> Applied to riscv-cache-for-next, thanks!
>
> [1/8] riscv: errata: Add StarFive JH7100 errata
> https://git.kernel.org/conor/c/64fc984a8a54
That's the one which also needs depends on !DMA_DIRECT_REMAP?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
2023-12-13 15:51 ` Geert Uytterhoeven
@ 2023-12-15 19:13 ` Emil Renner Berthing
0 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2023-12-15 19:13 UTC (permalink / raw)
To: Geert Uytterhoeven, Conor Dooley
Cc: linux-riscv, devicetree, linux-kernel, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Cristian Ciocaltea
Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@kernel.org> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> > > Now that the driver for the SiFive cache controller supports manual
> > > flushing as non-standard cache operations[1] we can add an errata option
> > > for the StarFive JH7100 SoC and update the device tree with the cache
> > > controller, dedicated DMA pool and add MMC nodes for the SD-card and
> > > wifi.
> > >
> > > This series needs the following commit in [1] to work properly:
> > >
> > > [...]
> >
> > Applied to riscv-cache-for-next, thanks!
> >
> > [1/8] riscv: errata: Add StarFive JH7100 errata
> > https://git.kernel.org/conor/c/64fc984a8a54
>
> That's the one which also needs depends on !DMA_DIRECT_REMAP?
Yes, thanks. I sent a fix now:
https://lore.kernel.org/linux-riscv/20231215190909.3722757-1-emil.renner.berthing@canonical.com/
/Emil
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing
` (8 preceding siblings ...)
2023-12-13 15:42 ` (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree Conor Dooley
@ 2023-12-13 15:53 ` Conor Dooley
9 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2023-12-13 15:53 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel, Emil Renner Berthing
Cc: conor, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Cristian Ciocaltea, Geert Uytterhoeven
From: Conor Dooley <conor.dooley@microchip.com>
On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> Now that the driver for the SiFive cache controller supports manual
> flushing as non-standard cache operations[1] we can add an errata option
> for the StarFive JH7100 SoC and update the device tree with the cache
> controller, dedicated DMA pool and add MMC nodes for the SD-card and
> wifi.
>
> This series needs the following commit in [1] to work properly:
>
> [...]
Applied to riscv-dt-for-next, thanks!
[2/8] riscv: dts: starfive: Group tuples in interrupt properties
https://git.kernel.org/conor/c/dd3c1b365fe9
[3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
https://git.kernel.org/conor/c/ba0074972ee9
[4/8] riscv: dts: starfive: Add JH7100 cache controller
https://git.kernel.org/conor/c/d4b95c445cab
[5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
https://git.kernel.org/conor/c/0a99b562e815
[6/8] riscv: dts: starfive: Add JH7100 MMC nodes
https://git.kernel.org/conor/c/a29bb6564e12
[7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards
https://git.kernel.org/conor/c/c548409cfe03
[8/8] riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
https://git.kernel.org/conor/c/56b10953da7e
Thanks,
Conor.
^ permalink raw reply [flat|nested] 14+ messages in thread