[PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

[PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

[Xingyu Wu]

This patch is to add the notifier for PLL0 clock and set the PLL0 rate
to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.

The first patch is to add the notifier for PLL0 clock. Setting the PLL0
rate need the son clock (cpu_root) to switch its parent clock to OSC
clock and switch it back after setting PLL0 rate. It need to use the
cpu_root clock from SYSCRG and register the notifier in the SYSCRG
driver.

The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
1.5GHz to fix the problem about the lower rate of CPUfreq on the
visionfive board. The cpu_core clock rate is set to 500MHz first to
ensure that the cpu frequency will not suddenly become high and the cpu
voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
The cpu voltage and frequency are then adjusted together by CPUfreq.

Changes since v3:
- Added the notifier for PLL0 clock.
- Set cpu_core rate in DTS

v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/

Changes since v2:
- Made the steps into the process into the process of setting PLL0 rate

v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/

Changes since v1:
- Added the fixes tag in the commit.

v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/

Xingyu Wu (2):
  clk: starfive: jh7110-sys: Add notifier for PLL clock
  riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by
    setting PLL0 rate to 1.5GHz

 .../jh7110-starfive-visionfive-2.dtsi         |  6 ++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
 3 files changed, 38 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

[Xingyu Wu]

Add notifier function for PLL clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL clock rate. After setting PLL
rate, it should be switched back to the original parent clock.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 8f5e5abfa178..adf62e4d94e4 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
 }
 EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
 
+/*
+ * This clock notifier is called when the rate of PLL0 clock is to be change,
+ * The cpu_root clock should save curent parent clock and swicth its parent
+ * clock to osc before PLL0 rate will be changed. And switch its parent clock
+ * back after PLL rate finished.
+ */
+static int jh7110_pll_clk_notifier_cb(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
+	struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
+	int ret = 0;
+
+	if (action == PRE_RATE_CHANGE) {
+		struct clk *osc = clk_get(priv->dev, "osc");
+
+		priv->original_clk = clk_get_parent(cpu_root);
+		ret = clk_set_parent(cpu_root, osc);
+		clk_put(osc);
+	} else if (action == POST_RATE_CHANGE) {
+		ret = clk_set_parent(cpu_root, priv->original_clk);
+	}
+
+	return notifier_from_errno(ret);
+}
+
 static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 {
 	struct jh71x0_clk_priv *priv;
@@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 		if (IS_ERR(priv->pll[0]))
 			return PTR_ERR(priv->pll[0]);
 	} else {
-		clk_put(pllclk);
+		priv->pll_clk_nb.notifier_call = jh7110_pll_clk_notifier_cb;
+		ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
+		if (ret)
+			return ret;
 		priv->pll[0] = NULL;
 	}
 
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index 23e052fc1549..e3f441393e48 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -114,6 +114,8 @@ struct jh71x0_clk_priv {
 	spinlock_t rmw_lock;
 	struct device *dev;
 	void __iomem *base;
+	struct clk *original_clk;
+	struct notifier_block pll_clk_nb;
 	struct clk_hw *pll[3];
 	struct jh71x0_clk reg[];
 };
-- 
2.25.1

Re: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

[Stephen Boyd]

Quoting Xingyu Wu (2024-04-09 20:31:47)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 8f5e5abfa178..adf62e4d94e4 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
>  }
>  EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
>  
> +/*
> + * This clock notifier is called when the rate of PLL0 clock is to be change,

s/change,/changed./

> + * The cpu_root clock should save curent parent clock and swicth its parent

s/swicth/switch/

> + * clock to osc before PLL0 rate will be changed. And switch its parent clock
> + * back after PLL rate finished.

RE: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

[Xingyu Wu]

On 10/04/2024 15:58, Stephen Boyd wrote:
> 
> Quoting Xingyu Wu (2024-04-09 20:31:47)
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > index 8f5e5abfa178..adf62e4d94e4 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct
> > jh71x0_clk_priv *priv,  }
> > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
> >
> > +/*
> > + * This clock notifier is called when the rate of PLL0 clock is to be
> > +change,
> 
> s/change,/changed./

Will fix.

> 
> > + * The cpu_root clock should save curent parent clock and swicth its
> > + parent
> 
> s/swicth/switch/

Will fix.

> 
> > + * clock to osc before PLL0 rate will be changed. And switch its
> > + parent clock
> > + * back after PLL rate finished.

Thanks,
Xingyu Wu

[PATCH v4 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

[Xingyu Wu]

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.

So PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi     | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 45b58b6f3df8..28981b267de4 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -390,6 +390,12 @@ spi_dev0: spi@0 {
 	};
 };
 
+&syscrg {
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+	assigned-clock-rates = <500000000>, <1500000000>;
+};
+
 &sysgpio {
 	i2c0_pins: i2c0-0 {
 		i2c-pins {
-- 
2.25.1

Re: [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

[Alexandre Ghiti]

Hi Xingyu,

On 10/04/2024 05:31, Xingyu Wu wrote:
> This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
>
> The first patch is to add the notifier for PLL0 clock. Setting the PLL0
> rate need the son clock (cpu_root) to switch its parent clock to OSC
> clock and switch it back after setting PLL0 rate. It need to use the
> cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> driver.
>
> The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> 1.5GHz to fix the problem about the lower rate of CPUfreq on the
> visionfive board. The cpu_core clock rate is set to 500MHz first to
> ensure that the cpu frequency will not suddenly become high and the cpu
> voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
> The cpu voltage and frequency are then adjusted together by CPUfreq.
>
> Changes since v3:
> - Added the notifier for PLL0 clock.
> - Set cpu_core rate in DTS
>
> v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/
>
> Changes since v2:
> - Made the steps into the process into the process of setting PLL0 rate
>
> v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/
>
> Changes since v1:
> - Added the fixes tag in the commit.
>
> v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/
>
> Xingyu Wu (2):
>    clk: starfive: jh7110-sys: Add notifier for PLL clock
>    riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by
>      setting PLL0 rate to 1.5GHz
>
>   .../jh7110-starfive-visionfive-2.dtsi         |  6 ++++
>   .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
>   drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
>   3 files changed, 38 insertions(+), 1 deletion(-)


I only took a quick look so I'm not sure: does patch 2 depend on patch 
1? In that case, I think the Fixes tag should be applied to both patches.

And as this is a fix, will you respin a new version soon for 6.9?

Thanks,

Alex

RE: [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

[Xingyu Wu]

On 25/04/2024 04:32, Alexandre Ghiti wrote:
> 
> Hi Xingyu,
> 
> On 10/04/2024 05:31, Xingyu Wu wrote:
> > This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> >
> > The first patch is to add the notifier for PLL0 clock. Setting the
> > PLL0 rate need the son clock (cpu_root) to switch its parent clock to
> > OSC clock and switch it back after setting PLL0 rate. It need to use
> > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> > driver.
> >
> > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> > 1.5GHz to fix the problem about the lower rate of CPUfreq on the
> > visionfive board. The cpu_core clock rate is set to 500MHz first to
> > ensure that the cpu frequency will not suddenly become high and the
> > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
> > The cpu voltage and frequency are then adjusted together by CPUfreq.
> >
> > Changes since v3:
> > - Added the notifier for PLL0 clock.
> > - Set cpu_core rate in DTS
> >
> > v3:
> > https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivet
> > ech.com/
> >
> > Changes since v2:
> > - Made the steps into the process into the process of setting PLL0
> > rate
> >
> > v2:
> > https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfive
> > tech.com/
> >
> > Changes since v1:
> > - Added the fixes tag in the commit.
> >
> > v1:
> > https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfive
> > tech.com/
> >
> > Xingyu Wu (2):
> >    clk: starfive: jh7110-sys: Add notifier for PLL clock
> >    riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by
> >      setting PLL0 rate to 1.5GHz
> >
> >   .../jh7110-starfive-visionfive-2.dtsi         |  6 ++++
> >   .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
> >   drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
> >   3 files changed, 38 insertions(+), 1 deletion(-)
> 
> 
> I only took a quick look so I'm not sure: does patch 2 depend on patch 1? In that
> case, I think the Fixes tag should be applied to both patches.

Hi Alex,

Yes, Patch 2 is dependent on patch 1. If patch 2 is applied alone, it does not work.
I will add the Fixes tag both patches.

> 
> And as this is a fix, will you respin a new version soon for 6.9?

Yes. I will send a new version of this patches.

Best regards,
Xingyu Wu