[PATCH 0/3] Add SFC support for RK3128

[PATCH 0/3] Add SFC support for RK3128

[Alex Bee]

This series adds support for the Serial Flash Controller (SFC) found in
RK3128 SoCs.

The existing driver can be used as-is.

Alex Bee (3):
  dt-bindings: clock: rk3128: Add HCLK_SFC
  clk: rockchip: Add HCLK_SFC for RK3128
  ARM: dts: rockchip: Add SFC for RK3128

 arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
 drivers/clk/rockchip/clk-rk3128.c      |  1 +
 include/dt-bindings/clock/rk3128-cru.h |  1 +
 3 files changed, 37 insertions(+)


base-commit: 234cb065ad82915ff8d06ce01e01c3e640b674d2
-- 
2.45.2

[PATCH 1/3] dt-bindings: clock: rk3128: Add HCLK_SFC

[Alex Bee]

Add a clock id for SFC's AHB clock.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
NB: I've added the new id at the top of existing HCLK's, since adding it at
the bottom would change CLK_NR_CLKS and therefore the ABI and there is
plenty of "free" ids between PCLK_MIPIPHY and HCLK_SPDIF.

 include/dt-bindings/clock/rk3128-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 1be455ba4985..a6bd7f13d7f8 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -119,6 +119,7 @@
 #define PCLK_MIPIPHY		370
 
 /* hclk gates */
+#define HCLK_SFC		439
 #define HCLK_SPDIF		440
 #define HCLK_GPS		441
 #define HCLK_USBHOST		442
-- 
2.45.2

Re: [PATCH 1/3] dt-bindings: clock: rk3128: Add HCLK_SFC

[Conor Dooley]

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On Wed, Jun 05, 2024 at 07:21:52PM +0200, Alex Bee wrote:
> Add a clock id for SFC's AHB clock.

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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Re: [PATCH 1/3] dt-bindings: clock: rk3128: Add HCLK_SFC

[Conor Dooley]

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On Wed, Jun 05, 2024 at 07:21:52PM +0200, Alex Bee wrote:
> Add a clock id for SFC's AHB clock.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
> NB: I've added the new id at the top of existing HCLK's, since adding it at
> the bottom would change CLK_NR_CLKS and therefore the ABI and there is
> plenty of "free" ids between PCLK_MIPIPHY and HCLK_SPDIF.

We've removed a bunch of things like "CLK_NR_CLKS" from bindings before
and advocate against adding them. Patches like this being the reason
why..

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Re: [PATCH 1/3] dt-bindings: clock: rk3128: Add HCLK_SFC

[Alex Bee]

Am 05.06.24 um 19:58 schrieb Conor Dooley:
> On Wed, Jun 05, 2024 at 07:21:52PM +0200, Alex Bee wrote:
>> Add a clock id for SFC's AHB clock.
>>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>> ---
>> NB: I've added the new id at the top of existing HCLK's, since adding it at
>> the bottom would change CLK_NR_CLKS and therefore the ABI and there is
>> plenty of "free" ids between PCLK_MIPIPHY and HCLK_SPDIF.
> We've removed a bunch of things like "CLK_NR_CLKS" from bindings before
> and advocate against adding them. Patches like this being the reason
> why..

Yeah, sure ... I thought removing it would be little out of scope for this
series. But as we are already having a helper for finding the "max id"  for
Rockchip clocks, I'll resend and remove that annoying macro and add the new
id at the bottom of the existing (where it belongs).

Alex

[PATCH 2/3] clk: rockchip: Add HCLK_SFC for RK3128

[Alex Bee]

The SFC IP exists only in RK3128 version of the SoC, thus the clock gets
added to rk3128_clk_branches.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/clk/rockchip/clk-rk3128.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index d076b7971f33..bc348fd0da92 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK2928_CLKGATE_CON(3), 15, GFLAGS),
 
+	GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
 	GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
 	GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
 };
-- 
2.45.2

[PATCH 3/3] ARM: dts: rockchip: Add SFC for RK3128

[Alex Bee]

Add the Serial Flash Controller and it's pincontrols.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index a7ab0904564f..22e2a35dedb1 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 {
 		status = "disabled";
 	};
 
+	sfc: spi@1020c000 {
+		compatible = "rockchip,sfc";
+		reg = <0x1020c000 0x8000>;
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		status = "disabled";
+	};
+
 	sdmmc: mmc@10214000 {
 		compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x10214000 0x4000>;
@@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 {
 			};
 		};
 
+		sfc {
+			sfc_bus2: sfc-bus2 {
+				rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+						<1 RK_PD1 3 &pcfg_pull_default>;
+			};
+
+			sfc_bus4: sfc-bus4 {
+				rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+						<1 RK_PD1 3 &pcfg_pull_default>,
+						<1 RK_PD2 3 &pcfg_pull_default>,
+						<1 RK_PD3 3 &pcfg_pull_default>;
+			};
+
+			sfc_clk: sfc-clk {
+				rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+			};
+
+			sfc_cs0: sfc-cs0 {
+				rockchip,pins = <2 RK_PA2 3 &pcfg_pull_default>;
+			};
+
+			sfc_cs1: sfc-cs1 {
+				rockchip,pins = <2 RK_PA3 3 &pcfg_pull_default>;
+			};
+		};
+
 		spdif {
 			spdif_tx: spdif-tx {
 				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
-- 
2.45.2