[PATCH 00/12] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform

[PATCH 00/12] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform

[Biju Das]

Hi all,

This patch series adds initial support for the Renesas RZ/G3E SoC and
RZ/G3E SMARC EVK platform. The RZ/G3E device is a general-purpose
microprocessor with a quad-core CA-55, single core CM-33, Ethos-U55 NPU
, Mali-G52 3-D Graphics and other peripherals.

Support for below list of blocks added on SoC DTSI (r9a09g047.dtsi):
 - EXT CLKs
 - 4X CA55
 - SCIF
 - CPG
 - GIC
 - ARMv8 Timer

This adds also support for the RZ/G3E SMARC EVK board
(r9a09g047e57-smarc.dts) and enable the following peripheral:
 - SCIF
 
Note:
 This patch series gives a boot console with serial driver support.
Later there is a plan to add support for SoC Identification using
SYSC driver and pin controller support were also added.
 
Test logs:
/ # uname -r
6.12.0-next-20241122-12513-g189628626a52

/ # cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 1
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 2
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 3
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

/ #

/ # cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3
 11:        436        539        467        446    GICv3  27 Level     arch_timer
 14:          0          0          0          0    GICv3 561 Level     11c01400.serial:rx err
 15:          0          0          0          0    GICv3 564 Level     11c01400.serial:rx full
 16:        391          0          0          0    GICv3 565 Level     11c01400.serial:tx empty
 17:          0          0          0          0    GICv3 562 Level     11c01400.serial:break
 18:         67          0          0          0    GICv3 566 Level     11c01400.serial:rx ready
 19:          0          0          0          0    GICv3 563 Level     11c01400.serial:tx end
IPI0:         3         12         12         25       Rescheduling interrupts
IPI1:       299        276        347         82       Function call interrupts
IPI2:         0          0          0          0       CPU stop interrupts
IPI3:         0          0          0          0       CPU stop NMIs
IPI4:         0          0          0          0       Timer broadcast interrupts
IPI5:         0          0          0          0       IRQ work interrupts
IPI6:         0          0          0          0       CPU backtrace interrupts
IPI7:         0          0          0          0       KGDB roundup interrupts
Err:          0
/ #

/ # cat /proc/meminfo
MemTotal:        3882652 kB
MemFree:         3846048 kB
MemAvailable:    3775780 kB

Biju Das (12):
  dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
  dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II
    EVK
  dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
  soc: renesas: Add RZ/G3E (R9A09G047) config option
  clk: renesas: Add support for RZ/G3E SoC
  clk: renesas: rzv2h-cpg: Add MSTOP support
  arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC
  arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM
  arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK
    board
  arm64: defconfig: Enable R9A09G047 SoC
  HACK-DO-NOT-APPLY-defconfig: Enable INIT RAMFS

 .../bindings/clock/renesas,rzv2h-cpg.yaml     |  15 +-
 .../bindings/serial/renesas,scif.yaml         |   5 +
 .../bindings/soc/renesas/renesas.yaml         |  17 +++
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 144 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi |  18 +++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  18 +++
 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi |  13 ++
 .../boot/dts/renesas/renesas-smarc2.dtsi      |  24 +++
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  28 ++++
 arch/arm64/configs/defconfig                  |   2 +
 drivers/clk/renesas/Kconfig                   |   7 +-
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a09g047-cpg.c           | 100 ++++++++++++
 drivers/clk/renesas/r9a09g057-cpg.c           | 117 +++++++++-----
 drivers/clk/renesas/rzv2h-cpg.c               |  98 +++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h               |  23 ++-
 drivers/soc/renesas/Kconfig                   |   5 +
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |  21 +++
 19 files changed, 604 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
 create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h

-- 
2.43.0

[PATCH 01/12] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif

[Biju Das]

Document scif bindings for the Renesas RZ/G3E (a.k.a r9a09g047) SoC.
SCIF interface in Renesas RZ/G3E is similar to the one available in
RZ/V2H.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,scif.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 51d9fb0f4763..8e82999e6acb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -83,6 +83,11 @@ properties:
 
       - const: renesas,scif-r9a09g057       # RZ/V2H(P)
 
+      - items:
+          - enum:
+              - renesas,scif-r9a09g047      # RZ/G3E
+          - const: renesas,scif-r9a09g057   # RZ/V2H fallback
+
   reg:
     maxItems: 1
 
-- 
2.43.0

[PATCH 02/12] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants

[Biju Das]

Document Renesas RZ/G3E (R9A09G047) SoC variants.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index b7acb65bdecd..7cc2bb97db13 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -525,6 +525,19 @@ properties:
               - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0
           - const: renesas,r9a09g011
 
+      - description: RZ/G3E (R9A09G047)
+        items:
+          - enum:
+              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
+              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
+          - const: renesas,r9a09g047
+
       - description: RZ/V2H(P) (R9A09G057)
         items:
           - enum:
-- 
2.43.0

[PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Biju Das]

Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based
on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK
consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
The SoM module sits on top of the carrier board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 7cc2bb97db13..1785142fc8da 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -527,6 +527,10 @@ properties:
 
       - description: RZ/G3E (R9A09G047)
         items:
+          - enum:
+              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+          - enum:
+              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
           - enum:
               - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
               - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
-- 
2.43.0

[PATCH 04/12] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG

[Biju Das]

Document the device tree bindings for the Renesas RZ/G3E SoC
Clock Pulse Generator (CPG).

Also define constants for the core clocks of the RZ/G3E SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/clock/renesas,rzv2h-cpg.yaml     | 15 +++++++------
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++
 2 files changed, 30 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index 926c503bed1f..c3fe76abd549 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -4,19 +4,22 @@
 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
-  and control of clock signals for the IP modules, generation and control of resets,
-  and control over booting, low power consumption and power supply domains.
+  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+  generation and control of clock signals for the IP modules, generation and
+  control of resets, and control over booting, low power consumption and power
+  supply domains.
 
 properties:
   compatible:
-    const: renesas,r9a09g057-cpg
+    enum:
+      - renesas,r9a09g047-cpg # RZ/G3E
+      - renesas,r9a09g057-cpg # RZ/V2H
 
   reg:
     maxItems: 1
@@ -37,7 +40,7 @@ properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
         a module number.  The module number is calculated as the CLKON register
         offset index multiplied by 16, plus the actual bit in the register
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
new file mode 100644
index 000000000000..5bcab7ca2bfc
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G047_SYS_0_PCLK			0
+#define R9A09G047_CA55_0_CORE_CLK0		1
+#define R9A09G047_CA55_0_CORE_CLK1		2
+#define R9A09G047_CA55_0_CORE_CLK2		3
+#define R9A09G047_CA55_0_CORE_CLK3		4
+#define R9A09G047_CA55_0_PERIPHCLK		5
+#define R9A09G047_CM33_CLK0			6
+#define R9A09G047_CST_0_SWCLKTCK		7
+#define R9A09G047_IOTOP_0_SHCLK			8
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
-- 
2.43.0

[PATCH 08/12] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC

[Biju Das]

Add the initial DTSI for the RZ/G3E SoC.
The files in this commit have the following meaning:
  - r9a09g047.dtsi:    RZ/G3E family SoC common parts
  - r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts
  - r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 144 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi |  18 +++
 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi |  13 ++
 3 files changed, 175 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
new file mode 100644
index 000000000000..4176b9aa6892
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g047";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_extal_clk: audio-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	qextal_clk: qextal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	rtxin_clk: rtxin-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller@10420000 {
+			compatible = "renesas,r9a09g047-cpg";
+			reg = <0 0x10420000 0 0x10000>;
+			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+			clock-names = "audio_extal", "rtxin", "qextal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		scif0: serial@11c01400 {
+			compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
+			reg = <0 0x11c01400 0 0x400>;
+			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+					  "tei", "tei-dri", "rxi-edge", "txi-edge";
+			clocks = <&cpg CPG_MOD 0x8f>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x95>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@14900000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x14900000 0 0x20000>,
+			      <0x0 0x14940000 0 0x80000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
new file mode 100644
index 000000000000..e50d9159e832
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";
+
+	cpus {
+		/delete-node/ cpu@200;
+		/delete-node/ cpu@300;
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
new file mode 100644
index 000000000000..98a5faebd47a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
-- 
2.43.0

[PATCH 09/12] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM

[Biju Das]

Add initial support for the RZ/G3E SMARC SoM with 4GB memory,
audio_extal, qextal and rtxin clks.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
new file mode 100644
index 000000000000..c8cf61545a5f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R9A09G047E57 SMARC SoM board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	compatible = "renesas,rzg3e-smarc", "renesas,r9a09g047e57", "renesas,r9a09g047";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* First 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0xf8000000>;
+	};
+};
+
+&audio_extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&qextal_clk {
+	clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+	clock-frequency = <32768>;
+};
-- 
2.43.0

[PATCH 10/12] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board

[Biju Das]

Add the initial device tree for the Renesas RZ/G3E SMARC EVK board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 ++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 18 ++++++++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 24 +++++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 97228a3cb99c..bf5b49f47ce8 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -140,6 +140,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
+
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
new file mode 100644
index 000000000000..d4d61bd03969
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SMARC EVK board
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g047e57.dtsi"
+#include "rzg3e-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
+	compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
+		     "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
new file mode 100644
index 000000000000..e378d55e6e9b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ SMARC Carrier-II Board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	model = "Renesas RZ SMARC Carrier-II Board";
+	compatible = "renesas,smarc2-evk";
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial3:115200n8";
+	};
+
+	aliases {
+		serial3 = &scif0;
+	};
+};
+
+&scif0 {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH 01/12] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif

[Conor Dooley]

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On Fri, Nov 22, 2024 at 12:45:37PM +0000, Biju Das wrote:
> Document scif bindings for the Renesas RZ/G3E (a.k.a r9a09g047) SoC.
> SCIF interface in Renesas RZ/G3E is similar to the one available in
> RZ/V2H.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 02/12] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants

[Conor Dooley]

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On Fri, Nov 22, 2024 at 12:45:38PM +0000, Biju Das wrote:
> Document Renesas RZ/G3E (R9A09G047) SoC variants.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Conor Dooley]

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On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based
> on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK
> consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> The SoM module sits on top of the carrier board.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index 7cc2bb97db13..1785142fc8da 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -527,6 +527,10 @@ properties:
>  
>        - description: RZ/G3E (R9A09G047)
>          items:
> +          - enum:
> +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> +          - enum:
> +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)

Why are these enums, when you have a single item in each?

>            - enum:
>                - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
>                - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
> -- 
> 2.43.0
> 

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Re: [PATCH 04/12] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG

[Conor Dooley]

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On Fri, Nov 22, 2024 at 12:45:40PM +0000, Biju Das wrote:
> Document the device tree bindings for the Renesas RZ/G3E SoC
> Clock Pulse Generator (CPG).
> 
> Also define constants for the core clocks of the RZ/G3E SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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RE: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 25 November 2024 18:52
> Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
> 
> On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based
> > on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK
> > consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > The SoM module sits on top of the carrier board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > index 7cc2bb97db13..1785142fc8da 100644
> > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > @@ -527,6 +527,10 @@ properties:
> >
> >        - description: RZ/G3E (R9A09G047)
> >          items:
> > +          - enum:
> > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > +          - enum:
> > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
> 
> Why are these enums, when you have a single item in each?

I just followed the style used in [1]

[1] https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devicetree/bindings/soc/renesas/renesas.yaml#L531

Other than that,

In future some vendors can add their RZ/G3E SoM's here

Or 

They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.

Cheers,
Biju

> 
> >            - enum:
> >                - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
> >                - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 +
> > Ethos-U55 (15mm BGA)
> > --
> > 2.43.0
> >

Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Conor Dooley]

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On Wed, Nov 27, 2024 at 12:34:42PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 25 November 2024 18:52
> > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
> > 
> > On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based
> > > on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK
> > > consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > > The SoM module sits on top of the carrier board.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > index 7cc2bb97db13..1785142fc8da 100644
> > > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > @@ -527,6 +527,10 @@ properties:
> > >
> > >        - description: RZ/G3E (R9A09G047)
> > >          items:
> > > +          - enum:
> > > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > > +          - enum:
> > > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
> > 
> > Why are these enums, when you have a single item in each?
> 
> I just followed the style used in [1]
> 
> [1] https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devicetree/bindings/soc/renesas/renesas.yaml#L531

It ain't the same though, since you additionally have the SoM.

> Other than that,
> 
> In future some vendors can add their RZ/G3E SoM's here

Only makes sense if their SoM is compatible with the smarc2-evk.

> Or 
> 
> They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.

But allowing this part does make sense.

> 
> Cheers,
> Biju
> 
> > 
> > >            - enum:
> > >                - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
> > >                - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 +
> > > Ethos-U55 (15mm BGA)
> > > --
> > > 2.43.0
> > >

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RE: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 27 November 2024 16:33
> Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
> 
> On Wed, Nov 27, 2024 at 12:34:42PM +0000, Biju Das wrote:
> > Hi Conor Dooley,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 25 November 2024 18:52
> > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > RZ/G3E SMARC SoM and Carrier-II EVK
> > >
> > > On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > > > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is
> > > > based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II
> > > > EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > > > The SoM module sits on top of the carrier board.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4
> > > > ++++
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > index 7cc2bb97db13..1785142fc8da 100644
> > > > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > @@ -527,6 +527,10 @@ properties:
> > > >
> > > >        - description: RZ/G3E (R9A09G047)
> > > >          items:
> > > > +          - enum:
> > > > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > > > +          - enum:
> > > > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
> > >
> > > Why are these enums, when you have a single item in each?
> >
> > I just followed the style used in [1]
> >
> > [1]
> > https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devicetr
> > ee/bindings/soc/renesas/renesas.yaml#L531
> 
> It ain't the same though, since you additionally have the SoM.
> 
> > Other than that,
> >
> > In future some vendors can add their RZ/G3E SoM's here
> 
> Only makes sense if their SoM is compatible with the smarc2-evk.

All our SMARC Modules and SMARC Carrier boards are SMARC compliant.

So, if anyone have a RZ/G3E SMARC SoM, that should work with SMARC2-EVK.

> 
> > Or
> >
> > They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.
> 
> But allowing this part does make sense.

We already have a use case for this example.

Renesas RZ/G3E SoM can work on both Renesas smarc-evk and smarc2-evk.

But we only officially support RZ/G3E SoM with SMARC2-EVK as it has multiple display support.

So, can I use const for both SoM and Carrier EVK as at the moment there is only
one?

Cheers,
Biju

Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Conor Dooley]

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On Wed, Nov 27, 2024 at 05:18:56PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 27 November 2024 16:33
> > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
> > 
> > On Wed, Nov 27, 2024 at 12:34:42PM +0000, Biju Das wrote:
> > > Hi Conor Dooley,
> > >
> > > Thanks for the feedback.
> > >
> > > > -----Original Message-----
> > > > From: Conor Dooley <conor@kernel.org>
> > > > Sent: 25 November 2024 18:52
> > > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > > RZ/G3E SMARC SoM and Carrier-II EVK
> > > >
> > > > On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > > > > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is
> > > > > based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II
> > > > > EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > > > > The SoM module sits on top of the carrier board.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4
> > > > > ++++
> > > > >  1 file changed, 4 insertions(+)
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > index 7cc2bb97db13..1785142fc8da 100644
> > > > > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > @@ -527,6 +527,10 @@ properties:
> > > > >
> > > > >        - description: RZ/G3E (R9A09G047)
> > > > >          items:
> > > > > +          - enum:
> > > > > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > > > > +          - enum:
> > > > > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
> > > >
> > > > Why are these enums, when you have a single item in each?
> > >
> > > I just followed the style used in [1]
> > >
> > > [1]
> > > https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devicetr
> > > ee/bindings/soc/renesas/renesas.yaml#L531
> > 
> > It ain't the same though, since you additionally have the SoM.
> > 
> > > Other than that,
> > >
> > > In future some vendors can add their RZ/G3E SoM's here
> > 
> > Only makes sense if their SoM is compatible with the smarc2-evk.
> 
> All our SMARC Modules and SMARC Carrier boards are SMARC compliant.

All of yours might be, but what you said was "some vendors".

> 
> So, if anyone have a RZ/G3E SMARC SoM, that should work with SMARC2-EVK.
> 
> > 
> > > Or
> > >
> > > They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.
> > 
> > But allowing this part does make sense.
> 
> We already have a use case for this example.
> 
> Renesas RZ/G3E SoM can work on both Renesas smarc-evk and smarc2-evk.
> 
> But we only officially support RZ/G3E SoM with SMARC2-EVK as it has multiple display support.
> 
> So, can I use const for both SoM and Carrier EVK as at the moment there is only
> one?

That is what I would do.

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RE: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Biju Das]

Hi Conor Dooley,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 27 November 2024 20:02
> Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
> 
> On Wed, Nov 27, 2024 at 05:18:56PM +0000, Biju Das wrote:
> > Hi Conor Dooley,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 27 November 2024 16:33
> > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > RZ/G3E SMARC SoM and Carrier-II EVK
> > >
> > > On Wed, Nov 27, 2024 at 12:34:42PM +0000, Biju Das wrote:
> > > > Hi Conor Dooley,
> > > >
> > > > Thanks for the feedback.
> > > >
> > > > > -----Original Message-----
> > > > > From: Conor Dooley <conor@kernel.org>
> > > > > Sent: 25 November 2024 18:52
> > > > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > > > RZ/G3E SMARC SoM and Carrier-II EVK
> > > > >
> > > > > On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > > > > > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which
> > > > > > is based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC
> > > > > > Carrier-II EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > > > > > The SoM module sits on top of the carrier board.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml |
> > > > > > 4
> > > > > > ++++
> > > > > >  1 file changed, 4 insertions(+)
> > > > > >
> > > > > > diff --git
> > > > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > index 7cc2bb97db13..1785142fc8da 100644
> > > > > > ---
> > > > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.ya
> > > > > > +++ ml
> > > > > > @@ -527,6 +527,10 @@ properties:
> > > > > >
> > > > > >        - description: RZ/G3E (R9A09G047)
> > > > > >          items:
> > > > > > +          - enum:
> > > > > > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > > > > > +          - enum:
> > > > > > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module
> > > > > > + (SoM)
> > > > >
> > > > > Why are these enums, when you have a single item in each?
> > > >
> > > > I just followed the style used in [1]
> > > >
> > > > [1]
> > > > https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devi
> > > > cetr
> > > > ee/bindings/soc/renesas/renesas.yaml#L531
> > >
> > > It ain't the same though, since you additionally have the SoM.
> > >
> > > > Other than that,
> > > >
> > > > In future some vendors can add their RZ/G3E SoM's here
> > >
> > > Only makes sense if their SoM is compatible with the smarc2-evk.
> >
> > All our SMARC Modules and SMARC Carrier boards are SMARC compliant.
> 
> All of yours might be, but what you said was "some vendors".

FYI, In the past, we have a requirement to validate smarc-evk before RZ/G2L SMARC
SoM available.

So, we just used a SMARC SoM based on RZ/G2N and tested smarc-evk ethernet interface(of course with small hw mods)

> 
> >
> > So, if anyone have a RZ/G3E SMARC SoM, that should work with SMARC2-EVK.
> >
> > >
> > > > Or
> > > >
> > > > They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.
> > >
> > > But allowing this part does make sense.
> >
> > We already have a use case for this example.
> >
> > Renesas RZ/G3E SoM can work on both Renesas smarc-evk and smarc2-evk.
> >
> > But we only officially support RZ/G3E SoM with SMARC2-EVK as it has multiple display support.
> >
> > So, can I use const for both SoM and Carrier EVK as at the moment
> > there is only one?
> 
> That is what I would do.

Geert, Please share your thoughts.

Cheers,
Biju

Re: [PATCH 03/12] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK

[Geert Uytterhoeven]

Hi Biju,

On Thu, Nov 28, 2024 at 7:52 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Conor Dooley <conor@kernel.org>
> > On Wed, Nov 27, 2024 at 05:18:56PM +0000, Biju Das wrote:
> > > > -----Original Message-----
> > > > From: Conor Dooley <conor@kernel.org>
> > > > Sent: 27 November 2024 16:33
> > > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > > RZ/G3E SMARC SoM and Carrier-II EVK
> > > >
> > > > On Wed, Nov 27, 2024 at 12:34:42PM +0000, Biju Das wrote:
> > > > > Hi Conor Dooley,
> > > > >
> > > > > Thanks for the feedback.
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Conor Dooley <conor@kernel.org>
> > > > > > Sent: 25 November 2024 18:52
> > > > > > Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document
> > > > > > RZ/G3E SMARC SoM and Carrier-II EVK
> > > > > >
> > > > > > On Fri, Nov 22, 2024 at 12:45:39PM +0000, Biju Das wrote:
> > > > > > > Document the Renesas RZ/G3E SMARC Carrier-II EVK board which
> > > > > > > is based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC
> > > > > > > Carrier-II EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
> > > > > > > The SoM module sits on top of the carrier board.
> > > > > > >
> > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/soc/renesas/renesas.yaml |
> > > > > > > 4
> > > > > > > ++++
> > > > > > >  1 file changed, 4 insertions(+)
> > > > > > >
> > > > > > > diff --git
> > > > > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > > index 7cc2bb97db13..1785142fc8da 100644
> > > > > > > ---
> > > > > > > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.ya
> > > > > > > +++ ml
> > > > > > > @@ -527,6 +527,10 @@ properties:
> > > > > > >
> > > > > > >        - description: RZ/G3E (R9A09G047)
> > > > > > >          items:
> > > > > > > +          - enum:
> > > > > > > +              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> > > > > > > +          - enum:
> > > > > > > +              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module
> > > > > > > + (SoM)
> > > > > >
> > > > > > Why are these enums, when you have a single item in each?
> > > > >
> > > > > I just followed the style used in [1]
> > > > >
> > > > > [1]
> > > > > https://elixir.bootlin.com/linux/v6.12.1/source/Documentation/devi
> > > > > cetr
> > > > > ee/bindings/soc/renesas/renesas.yaml#L531
> > > >
> > > > It ain't the same though, since you additionally have the SoM.
> > > >
> > > > > Other than that,
> > > > >
> > > > > In future some vendors can add their RZ/G3E SoM's here
> > > >
> > > > Only makes sense if their SoM is compatible with the smarc2-evk.
> > >
> > > All our SMARC Modules and SMARC Carrier boards are SMARC compliant.
> >
> > All of yours might be, but what you said was "some vendors".
>
> FYI, In the past, we have a requirement to validate smarc-evk before RZ/G2L SMARC
> SoM available.
>
> So, we just used a SMARC SoM based on RZ/G2N and tested smarc-evk ethernet interface(of course with small hw mods)

Cool!

> > > So, if anyone have a RZ/G3E SMARC SoM, that should work with SMARC2-EVK.
> > >
> > > > >
> > > > > They can use Renesas RZ/G3E SMARC module and use their custom carrier boards.
> > > >
> > > > But allowing this part does make sense.
> > >
> > > We already have a use case for this example.
> > >
> > > Renesas RZ/G3E SoM can work on both Renesas smarc-evk and smarc2-evk.
> > >
> > > But we only officially support RZ/G3E SoM with SMARC2-EVK as it has multiple display support.
> > >
> > > So, can I use const for both SoM and Carrier EVK as at the moment
> > > there is only one?
> >
> > That is what I would do.
>
> Geert, Please share your thoughts.

I prefer the enum, as it causes less churn when adding more entries
later.  Cfr. using a comma after the last entry in a C array, so new
entries can be appended later, without touching existing lines.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 04/12] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG

[Biju Das]

Hi Conor and Geert,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 22 November 2024 12:46
> Subject: [PATCH 04/12] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
> 
> Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG).
> 
> Also define constants for the core clocks of the RZ/G3E SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     | 15 +++++++------
>  .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++
>  2 files changed, 30 insertions(+), 6 deletions(-)  create mode 100644 include/dt-
> bindings/clock/renesas,r9a09g047-cpg.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> index 926c503bed1f..c3fe76abd549 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -4,19 +4,22 @@
>  $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
> 
> -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
> 
>  maintainers:
>    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
>  description:
> -  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
> -  and control of clock signals for the IP modules, generation and control of resets,
> -  and control over booting, low power consumption and power supply domains.
> +  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator)
> + handles  generation and control of clock signals for the IP modules,
> + generation and  control of resets, and control over booting, low power
> + consumption and power  supply domains.
> 
>  properties:
>    compatible:
> -    const: renesas,r9a09g057-cpg
> +    enum:
> +      - renesas,r9a09g047-cpg # RZ/G3E
> +      - renesas,r9a09g057-cpg # RZ/V2H
> 
>    reg:
>      maxItems: 1
> @@ -37,7 +40,7 @@ properties:
>      description: |
>        - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
>          and a core clock reference, as defined in
> -        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
> +        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
>        - For module clocks, the two clock specifier cells must be "CPG_MOD" and
>          a module number.  The module number is calculated as the CLKON register
>          offset index multiplied by 16, plus the actual bit in the register diff --git a/include/dt-
> bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
> new file mode 100644
> index 000000000000..5bcab7ca2bfc
> --- /dev/null
> +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
> +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* Core Clock list */
> +#define R9A09G047_SYS_0_PCLK			0
> +#define R9A09G047_CA55_0_CORE_CLK0		1
> +#define R9A09G047_CA55_0_CORE_CLK1		2
> +#define R9A09G047_CA55_0_CORE_CLK2		3
> +#define R9A09G047_CA55_0_CORE_CLK3		4

Typo here based on the based on "RZG3E_ClockList_rev1.0_na.xlsx"
CORE_CLK*-> CORECLK*

I will fix this while sending v2.

Cheers,
Biju