From: Krzysztof Kozlowski <krzk@kernel.org>
To: Varadarajan Narayanan <quic_varada@quicinc.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org,
konradybcio@kernel.org, linux-arm-msm@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v13 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
Date: Fri, 14 Mar 2025 08:57:50 +0100 [thread overview]
Message-ID: <20250314-resolute-slim-waxbill-eaa9ee@krzk-bin> (raw)
In-Reply-To: <Z9LGti0cdg9Sj6xa@hu-varada-blr.qualcomm.com>
On Thu, Mar 13, 2025 at 05:21:18PM +0530, Varadarajan Narayanan wrote:
> On Thu, Mar 13, 2025 at 12:01:54PM +0100, Krzysztof Kozlowski wrote:
> > On 13/03/2025 09:05, Varadarajan Narayanan wrote:
> > > Append the MHI register range to IPQ9574. This is an optional range used
> >
> > Same question, you still did not answer - does hardware have this range?
> > Which hardware has it?
>
> Yes. All three (ipq6018, ipq8074, ipq9574) have this range.
Then explain in the commit msg that you complete the hardware
description for these SoCs.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-14 7:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-13 8:05 [PATCH v13 0/4] Add PCIe support for Qualcomm IPQ5332 Varadarajan Narayanan
2025-03-13 8:05 ` [PATCH v13 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574 Varadarajan Narayanan
2025-03-13 11:01 ` Krzysztof Kozlowski
2025-03-13 11:51 ` Varadarajan Narayanan
2025-03-14 7:57 ` Krzysztof Kozlowski [this message]
2025-03-13 8:05 ` [PATCH v13 2/4] arm64: dts: qcom: ipq9574: Add MHI to pcie nodes Varadarajan Narayanan
2025-03-13 8:05 ` [PATCH v13 3/4] arm64: dts: qcom: ipq5332: Add PCIe related nodes Varadarajan Narayanan
2025-03-13 8:06 ` [PATCH v13 4/4] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Varadarajan Narayanan
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