From: Ben Zong-You Xie <ben717@andestech.com>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <tglx@linutronix.de>,
<daniel.lezcano@linaro.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <tim609@andestech.com>,
Ben Zong-You Xie <ben717@andestech.com>
Subject: [PATCH v3 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
Date: Tue, 13 May 2025 17:49:26 +0800 [thread overview]
Message-ID: <20250513094933.1631493-3-ben717@andestech.com> (raw)
In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com>
Add DT binding documentation for the Andes QiLai SoC and the
Voyager development board.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
.../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++
MAINTAINERS | 5 ++++
2 files changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documentation/devicetree/bindings/riscv/andes.yaml
new file mode 100644
index 000000000000..aa1edf1fdec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/andes.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/andes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes SoC-based boards
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+description:
+ Andes SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - andestech,voyager
+ - const: andestech,qilai
+
+additionalProperties: true
diff --git a/MAINTAINERS b/MAINTAINERS
index 96b827049501..a0ccac1cca29 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20725,6 +20725,11 @@ F: drivers/irqchip/irq-riscv-intc.c
F: include/linux/irqchip/riscv-aplic.h
F: include/linux/irqchip/riscv-imsic.h
+RISC-V ANDES SoC Support
+M: Ben Zong-You Xie <ben717@andestech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/riscv/andes.yaml
+
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
--
2.34.1
next prev parent reply other threads:[~2025-05-13 9:50 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 9:49 [PATCH v3 0/9] add Voyager board support Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-13 9:49 ` Ben Zong-You Xie [this message]
2025-05-13 9:49 ` [PATCH v3 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 6/9] dt-bindings: cache: add QiLai compatible to ax45mp Ben Zong-You Xie
2025-05-13 15:53 ` Conor Dooley
2025-05-13 9:49 ` [PATCH v3 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-13 9:49 ` [PATCH v3 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
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