[PATCH v3 6/9] dt-bindings: cache: add QiLai compatible to ax45mp

[Ben Zong-You Xie <ben717@andestech.com>]

Add a new compatible string for ax45mp-cache on QiLai SoC.

Also, add allOf constraints to enforce specific cache-sets and cache-size
values for each compatible string.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 .../cache/andestech,ax45mp-cache.yaml         | 52 +++++++++++++++++--
 1 file changed, 47 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index df8bba14f758..dc03ffae6c9f 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -28,7 +28,9 @@ select:
 properties:
   compatible:
     items:
-      - const: renesas,r9a07g043f-ax45mp-cache
+      - enum:
+          - andestech,qilai-ax45mp-cache
+          - renesas,r9a07g043f-ax45mp-cache
       - const: andestech,ax45mp-cache
       - const: cache
 
@@ -44,11 +46,9 @@ properties:
   cache-level:
     const: 2
 
-  cache-sets:
-    enum: [1024, 2048]
+  cache-sets: true
 
-  cache-size:
-    enum: [131072, 262144, 524288, 1048576, 2097152]
+  cache-size: true
 
   cache-unified: true
 
@@ -66,7 +66,49 @@ required:
   - cache-size
   - cache-unified
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: andestech,qilai-ax45mp-cache
+
+    then:
+      properties:
+        cache-sets:
+          const: 2048
+        cache-size:
+          const: 2097152
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043f-ax45mp-cache
+
+    then:
+      properties:
+        cache-sets:
+          const: 1024
+        cache-size:
+          const: 262144
+
 examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    l2_cache: cache-controller@200000 {
+        compatible = "andestech,qilai-ax45mp-cache", "andestech,ax45mp-cache",
+                     "cache";
+        reg = <0x00200000 0x100000>;
+        interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+        cache-line-size = <64>;
+        cache-level = <2>;
+        cache-sets = <2048>;
+        cache-size = <2097152>;
+        cache-unified;
+    };
+
   - |
     #include <dt-bindings/interrupt-controller/irq.h>
 
-- 
2.34.1