[PATCH v2 1/6] iio: adc: ad4080: fix chip identification

[PATCH v2 1/6] iio: adc: ad4080: fix chip identification

[Antoniu Miclaus]

Fix AD4080 chip identification by using the correct 16-bit product ID
(0x0050) instead of GENMASK(2, 0). Update the chip reading logic to
use regmap_bulk_read to read both PRODUCT_ID_L and PRODUCT_ID_H
registers and combine them into a 16-bit value.

The original implementation was incorrectly reading only 3 bits,
which would not correctly identify the AD4080 chip.

Fixes: 6b31ba1811b6 ("iio: adc: ad4080: add driver support")
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v2:
 - add the chip id handling into a separate commit.
 - use regmap_bulk_read.
 drivers/iio/adc/ad4080.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
index 6e61787ed321..b80560aebe2d 100644
--- a/drivers/iio/adc/ad4080.c
+++ b/drivers/iio/adc/ad4080.c
@@ -125,7 +125,7 @@
 
 /* Miscellaneous Definitions */
 #define AD4080_SPI_READ						BIT(7)
-#define AD4080_CHIP_ID						GENMASK(2, 0)
+#define AD4080_CHIP_ID						0x0050
 
 #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
 
@@ -458,10 +458,11 @@ static int ad4080_setup(struct iio_dev *indio_dev)
 	if (ret)
 		return ret;
 
-	ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id);
+	ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id, 2);
 	if (ret)
 		return ret;
 
+	id = get_unaligned_le16(&id);
 	if (id != AD4080_CHIP_ID)
 		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
 
-- 
2.43.0

[PATCH v2 2/6] iio: adc: ad4080: prepare driver for multi-part support

[Antoniu Miclaus]

Refactor the ad4080 driver to support multiple ADC variants with
different resolution bits and LVDS CNV clock count maximums.

Changes:
- Add lvds_cnv_clk_cnt_max field to chip_info structure
- Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits
- Make LVDS CNV clock count configurable per chip variant
- Use chip_info->product_id for chip identification comparison

This prepares the infrastructure for adding support for additional
ADC parts with different specifications while maintaining backward
compatibility with existing AD4080 functionality.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v2:
 - allign all the \ to the left in the channel definition.
 drivers/iio/adc/ad4080.c | 42 ++++++++++++++++++++++------------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
index b80560aebe2d..fa15b8f63b8a 100644
--- a/drivers/iio/adc/ad4080.c
+++ b/drivers/iio/adc/ad4080.c
@@ -167,6 +167,7 @@ struct ad4080_chip_info {
 	const unsigned int (*scale_table)[2];
 	const struct iio_chan_spec *channels;
 	unsigned int num_channels;
+	unsigned int lvds_cnv_clk_cnt_max;
 };
 
 struct ad4080_state {
@@ -414,23 +415,25 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
 	{ }
 };
 
-static const struct iio_chan_spec ad4080_channel = {
-	.type = IIO_VOLTAGE,
-	.indexed = 1,
-	.channel = 0,
-	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),
-	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
-			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
-	.info_mask_shared_by_all_available =
-			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
-	.ext_info = ad4080_ext_info,
-	.scan_index = 0,
-	.scan_type = {
-		.sign = 's',
-		.realbits = 20,
-		.storagebits = 32,
-	},
-};
+#define AD4080_CHANNEL_DEFINE(bits, storage) {				\
+	.type = IIO_VOLTAGE,						\
+	.indexed = 1,							\
+	.channel = 0,							\
+	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),			\
+	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\
+			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
+	.info_mask_shared_by_all_available =				\
+			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
+	.ext_info = ad4080_ext_info,					\
+	.scan_index = 0,						\
+	.scan_type = {							\
+		.sign = 's',						\
+		.realbits = (bits),					\
+		.storagebits = (storage),				\
+	},								\
+}
+
+static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32);
 
 static const struct ad4080_chip_info ad4080_chip_info = {
 	.name = "ad4080",
@@ -439,6 +442,7 @@ static const struct ad4080_chip_info ad4080_chip_info = {
 	.num_scales = ARRAY_SIZE(ad4080_scale_table),
 	.num_channels = 1,
 	.channels = &ad4080_channel,
+	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
 };
 
 static int ad4080_setup(struct iio_dev *indio_dev)
@@ -463,7 +467,7 @@ static int ad4080_setup(struct iio_dev *indio_dev)
 		return ret;
 
 	id = get_unaligned_le16(&id);
-	if (id != AD4080_CHIP_ID)
+	if (id != st->info->product_id)
 		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
 
 	ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A,
@@ -489,7 +493,7 @@ static int ad4080_setup(struct iio_dev *indio_dev)
 				 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
 				 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
 				 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
-					    AD4080_LVDS_CNV_CLK_CNT_MAX));
+					    st->info->lvds_cnv_clk_cnt_max));
 	if (ret)
 		return ret;
 
-- 
2.43.0

[PATCH v2 3/6] dt-bindings: iio: adc: adi,ad4080: add support for AD4084

[Antoniu Miclaus]

Add device tree binding support for the AD4084 16-bit SAR ADC.
Add adi,ad4084 to the compatible enum.

A fallback compatible string to adi,ad4080 is not appropriate as the
AD4084 has different resolution (16-bit vs 20-bit) and LVDS CNV clock
count maximum (2 vs 7), requiring different driver configuration.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 - improve commit description with respect to fallback compatibility.
 Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
index ed849ba1b77b..c4c5d208f502 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
@@ -26,6 +26,7 @@ properties:
   compatible:
     enum:
       - adi,ad4080
+      - adi,ad4084
 
   reg:
     maxItems: 1
-- 
2.43.0

[PATCH v2 4/6] iio: adc: ad4080: add support for AD4084

[Antoniu Miclaus]

Add support for AD4084 16-bit SAR ADC. The AD4084 differs from
AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count
maximum (2 vs 7).

Changes:
- Add AD4084_CHIP_ID definition (0x0054)
- Create ad4084_channel with 16-bit resolution and storage
- Add ad4084_chip_info with appropriate configuration
- Register AD4084 in device ID and OF match tables

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
no changes in v2.
 drivers/iio/adc/ad4080.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
index fa15b8f63b8a..a68d7fa9f977 100644
--- a/drivers/iio/adc/ad4080.c
+++ b/drivers/iio/adc/ad4080.c
@@ -126,6 +126,7 @@
 /* Miscellaneous Definitions */
 #define AD4080_SPI_READ						BIT(7)
 #define AD4080_CHIP_ID						0x0050
+#define AD4084_CHIP_ID						0x0054
 
 #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
 
@@ -435,6 +436,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
 
 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32);
 
+static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16);
+
 static const struct ad4080_chip_info ad4080_chip_info = {
 	.name = "ad4080",
 	.product_id = AD4080_CHIP_ID,
@@ -445,6 +448,16 @@ static const struct ad4080_chip_info ad4080_chip_info = {
 	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
 };
 
+static const struct ad4080_chip_info ad4084_chip_info = {
+	.name = "ad4084",
+	.product_id = AD4084_CHIP_ID,
+	.scale_table = ad4080_scale_table,
+	.num_scales = ARRAY_SIZE(ad4080_scale_table),
+	.num_channels = 1,
+	.channels = &ad4084_channel,
+	.lvds_cnv_clk_cnt_max = 2,
+};
+
 static int ad4080_setup(struct iio_dev *indio_dev)
 {
 	struct ad4080_state *st = iio_priv(indio_dev);
@@ -598,12 +611,14 @@ static int ad4080_probe(struct spi_device *spi)
 
 static const struct spi_device_id ad4080_id[] = {
 	{ "ad4080", (kernel_ulong_t)&ad4080_chip_info },
+	{ "ad4084", (kernel_ulong_t)&ad4084_chip_info },
 	{ }
 };
 MODULE_DEVICE_TABLE(spi, ad4080_id);
 
 static const struct of_device_id ad4080_of_match[] = {
 	{ .compatible = "adi,ad4080", &ad4080_chip_info },
+	{ .compatible = "adi,ad4084", &ad4084_chip_info },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ad4080_of_match);
-- 
2.43.0

[PATCH v2 5/6] dt-bindings: iio: adc: adi,ad4080: add support for AD4081

[Antoniu Miclaus]

Add device tree binding support for the AD4081 20-bit SAR ADC.
Add adi,ad4081 to the compatible enum.

A fallback compatible string to adi,ad4080 is not appropriate as the
AD4081 has a different LVDS CNV clock count maximum (2 vs 7), requiring
different driver configuration.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v2:
 - improve commit description with respect to fallback compatibility.
 Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
index c4c5d208f502..a9fa068189ea 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
@@ -26,6 +26,7 @@ properties:
   compatible:
     enum:
       - adi,ad4080
+      - adi,ad4081
       - adi,ad4084
 
   reg:
-- 
2.43.0

[PATCH v2 6/6] iio: adc: ad4080: add support for AD4081

[Antoniu Miclaus]

Add support for AD4081 20-bit SAR ADC. The AD4081 has the same
resolution as AD4080 (20-bit) but differs in LVDS CNV clock count
maximum (2 vs 7).

Changes:
- Add AD4081_CHIP_ID definition (0x0051)
- Create ad4081_channel with 20-bit resolution and 32-bit storage
- Add ad4081_chip_info with lvds_cnv_clk_cnt_max = 2
- Register AD4081 in device ID and OF match tables

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
no changes in v2.
 drivers/iio/adc/ad4080.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
index a68d7fa9f977..0dcbf175523c 100644
--- a/drivers/iio/adc/ad4080.c
+++ b/drivers/iio/adc/ad4080.c
@@ -126,6 +126,7 @@
 /* Miscellaneous Definitions */
 #define AD4080_SPI_READ						BIT(7)
 #define AD4080_CHIP_ID						0x0050
+#define AD4081_CHIP_ID						0x0051
 #define AD4084_CHIP_ID						0x0054
 
 #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
@@ -436,6 +437,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
 
 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32);
 
+static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32);
+
 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16);
 
 static const struct ad4080_chip_info ad4080_chip_info = {
@@ -448,6 +451,16 @@ static const struct ad4080_chip_info ad4080_chip_info = {
 	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
 };
 
+static const struct ad4080_chip_info ad4081_chip_info = {
+	.name = "ad4081",
+	.product_id = AD4081_CHIP_ID,
+	.scale_table = ad4080_scale_table,
+	.num_scales = ARRAY_SIZE(ad4080_scale_table),
+	.num_channels = 1,
+	.channels = &ad4081_channel,
+	.lvds_cnv_clk_cnt_max = 2,
+};
+
 static const struct ad4080_chip_info ad4084_chip_info = {
 	.name = "ad4084",
 	.product_id = AD4084_CHIP_ID,
@@ -611,6 +624,7 @@ static int ad4080_probe(struct spi_device *spi)
 
 static const struct spi_device_id ad4080_id[] = {
 	{ "ad4080", (kernel_ulong_t)&ad4080_chip_info },
+	{ "ad4081", (kernel_ulong_t)&ad4081_chip_info },
 	{ "ad4084", (kernel_ulong_t)&ad4084_chip_info },
 	{ }
 };
@@ -618,6 +632,7 @@ MODULE_DEVICE_TABLE(spi, ad4080_id);
 
 static const struct of_device_id ad4080_of_match[] = {
 	{ .compatible = "adi,ad4080", &ad4080_chip_info },
+	{ .compatible = "adi,ad4081", &ad4081_chip_info },
 	{ .compatible = "adi,ad4084", &ad4084_chip_info },
 	{ }
 };
-- 
2.43.0

Re: [PATCH v2 1/6] iio: adc: ad4080: fix chip identification

[Nuno Sá]

Hi Antoniu,

I think that for a series like this you should include a cover letter...

On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote:
> Fix AD4080 chip identification by using the correct 16-bit product ID
> (0x0050) instead of GENMASK(2, 0). Update the chip reading logic to
> use regmap_bulk_read to read both PRODUCT_ID_L and PRODUCT_ID_H
> registers and combine them into a 16-bit value.
> 
> The original implementation was incorrectly reading only 3 bits,
> which would not correctly identify the AD4080 chip.
> 
> Fixes: 6b31ba1811b6 ("iio: adc: ad4080: add driver support")
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v2:
>  - add the chip id handling into a separate commit.
>  - use regmap_bulk_read.
>  drivers/iio/adc/ad4080.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index 6e61787ed321..b80560aebe2d 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
> @@ -125,7 +125,7 @@
>  
>  /* Miscellaneous Definitions */
>  #define
> AD4080_SPI_READ						BIT(7)
> -#define AD4080_CHIP_ID						GENMASK(2, 0)
> +#define AD4080_CHIP_ID						0x0050
>  
>  #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
>  
> @@ -458,10 +458,11 @@ static int ad4080_setup(struct iio_dev *indio_dev)
>  	if (ret)
>  		return ret;
>  
> -	ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id);
> +	ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id, 2);
>  	if (ret)
>  		return ret;
>  
> +	id = get_unaligned_le16(&id);

Being id an 'unsigned int' I'm not really sure the above will work on big endian
machines as we should only populate the 2 MSB, right? But independent of that,
id is only being used in here so I would use proper __le16 (and u16) and
le16_to_cpu().

- Nuno Sá

>  	if (id != AD4080_CHIP_ID)
>  		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
>  

Re: [PATCH v2 2/6] iio: adc: ad4080: prepare driver for multi-part support

[Nuno Sá]

On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote:
> Refactor the ad4080 driver to support multiple ADC variants with
> different resolution bits and LVDS CNV clock count maximums.
> 
> Changes:
> - Add lvds_cnv_clk_cnt_max field to chip_info structure
> - Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits
> - Make LVDS CNV clock count configurable per chip variant
> - Use chip_info->product_id for chip identification comparison
> 
> This prepares the infrastructure for adding support for additional
> ADC parts with different specifications while maintaining backward
> compatibility with existing AD4080 functionality.
> 
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---

Reviewed-by: Nuno Sá <nuno.sa@analog.com>

> changes in v2:
>  - allign all the \ to the left in the channel definition.
>  drivers/iio/adc/ad4080.c | 42 ++++++++++++++++++++++------------------
>  1 file changed, 23 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index b80560aebe2d..fa15b8f63b8a 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
> @@ -167,6 +167,7 @@ struct ad4080_chip_info {
>  	const unsigned int (*scale_table)[2];
>  	const struct iio_chan_spec *channels;
>  	unsigned int num_channels;
> +	unsigned int lvds_cnv_clk_cnt_max;
>  };
>  
>  struct ad4080_state {
> @@ -414,23 +415,25 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] =
> {
>  	{ }
>  };
>  
> -static const struct iio_chan_spec ad4080_channel = {
> -	.type = IIO_VOLTAGE,
> -	.indexed = 1,
> -	.channel = 0,
> -	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),
> -	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
> -			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
> -	.info_mask_shared_by_all_available =
> -			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
> -	.ext_info = ad4080_ext_info,
> -	.scan_index = 0,
> -	.scan_type = {
> -		.sign = 's',
> -		.realbits = 20,
> -		.storagebits = 32,
> -	},
> -};
> +#define AD4080_CHANNEL_DEFINE(bits, storage) {				\
> +	.type = IIO_VOLTAGE,						\
> +	.indexed = 1,							\
> +	.channel = 0,							\
> +	.info_mask_separate =
> BIT(IIO_CHAN_INFO_SCALE),			\
> +	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\
> +			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
> +	.info_mask_shared_by_all_available =				\
> +			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
> +	.ext_info = ad4080_ext_info,					\
> +	.scan_index = 0,						\
> +	.scan_type = {							\
> +		.sign = 's',						\
> +		.realbits = (bits),					\
> +		.storagebits = (storage),				\
> +	},								\
> +}
> +
> +static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20,
> 32);
>  
>  static const struct ad4080_chip_info ad4080_chip_info = {
>  	.name = "ad4080",
> @@ -439,6 +442,7 @@ static const struct ad4080_chip_info ad4080_chip_info = {
>  	.num_scales = ARRAY_SIZE(ad4080_scale_table),
>  	.num_channels = 1,
>  	.channels = &ad4080_channel,
> +	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
>  };
>  
>  static int ad4080_setup(struct iio_dev *indio_dev)
> @@ -463,7 +467,7 @@ static int ad4080_setup(struct iio_dev *indio_dev)
>  		return ret;
>  
>  	id = get_unaligned_le16(&id);
> -	if (id != AD4080_CHIP_ID)
> +	if (id != st->info->product_id)
>  		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
>  
>  	ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A,
> @@ -489,7 +493,7 @@ static int ad4080_setup(struct iio_dev *indio_dev)
>  				 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
>  				
> AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
>  				
> FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
> -					    AD4080_LVDS_CNV_CLK_CNT_MAX));
> +					    st->info->lvds_cnv_clk_cnt_max));
>  	if (ret)
>  		return ret;
>  

Re: [PATCH v2 4/6] iio: adc: ad4080: add support for AD4084

[Nuno Sá]

On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote:
> Add support for AD4084 16-bit SAR ADC. The AD4084 differs from
> AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count
> maximum (2 vs 7).
> 
> Changes:
> - Add AD4084_CHIP_ID definition (0x0054)
> - Create ad4084_channel with 16-bit resolution and storage
> - Add ad4084_chip_info with appropriate configuration
> - Register AD4084 in device ID and OF match tables
> 
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---

Reviewed-by: Nuno Sá <nuno.sa@analog.com>

> no changes in v2.
>  drivers/iio/adc/ad4080.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index fa15b8f63b8a..a68d7fa9f977 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
> @@ -126,6 +126,7 @@
>  /* Miscellaneous Definitions */
>  #define
> AD4080_SPI_READ						BIT(7)
>  #define AD4080_CHIP_ID						0x0050
> +#define AD4084_CHIP_ID						0x0054
>  
>  #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
>  
> @@ -435,6 +436,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
>  
>  static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20,
> 32);
>  
> +static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16,
> 16);
> +
>  static const struct ad4080_chip_info ad4080_chip_info = {
>  	.name = "ad4080",
>  	.product_id = AD4080_CHIP_ID,
> @@ -445,6 +448,16 @@ static const struct ad4080_chip_info ad4080_chip_info = {
>  	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
>  };
>  
> +static const struct ad4080_chip_info ad4084_chip_info = {
> +	.name = "ad4084",
> +	.product_id = AD4084_CHIP_ID,
> +	.scale_table = ad4080_scale_table,
> +	.num_scales = ARRAY_SIZE(ad4080_scale_table),
> +	.num_channels = 1,
> +	.channels = &ad4084_channel,
> +	.lvds_cnv_clk_cnt_max = 2,
> +};
> +
>  static int ad4080_setup(struct iio_dev *indio_dev)
>  {
>  	struct ad4080_state *st = iio_priv(indio_dev);
> @@ -598,12 +611,14 @@ static int ad4080_probe(struct spi_device *spi)
>  
>  static const struct spi_device_id ad4080_id[] = {
>  	{ "ad4080", (kernel_ulong_t)&ad4080_chip_info },
> +	{ "ad4084", (kernel_ulong_t)&ad4084_chip_info },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(spi, ad4080_id);
>  
>  static const struct of_device_id ad4080_of_match[] = {
>  	{ .compatible = "adi,ad4080", &ad4080_chip_info },
> +	{ .compatible = "adi,ad4084", &ad4084_chip_info },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, ad4080_of_match);

Re: [PATCH v2 6/6] iio: adc: ad4080: add support for AD4081

[Nuno Sá]

On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote:
> Add support for AD4081 20-bit SAR ADC. The AD4081 has the same
> resolution as AD4080 (20-bit) but differs in LVDS CNV clock count
> maximum (2 vs 7).
> 
> Changes:
> - Add AD4081_CHIP_ID definition (0x0051)
> - Create ad4081_channel with 20-bit resolution and 32-bit storage
> - Add ad4081_chip_info with lvds_cnv_clk_cnt_max = 2
> - Register AD4081 in device ID and OF match tables
> 
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---

Reviewed-by: Nuno Sá <nuno.sa@analog.com>

> no changes in v2.
>  drivers/iio/adc/ad4080.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index a68d7fa9f977..0dcbf175523c 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
> @@ -126,6 +126,7 @@
>  /* Miscellaneous Definitions */
>  #define
> AD4080_SPI_READ						BIT(7)
>  #define AD4080_CHIP_ID						0x0050
> +#define AD4081_CHIP_ID						0x0051
>  #define AD4084_CHIP_ID						0x0054
>  
>  #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
> @@ -436,6 +437,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
>  
>  static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20,
> 32);
>  
> +static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20,
> 32);
> +
>  static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16,
> 16);
>  
>  static const struct ad4080_chip_info ad4080_chip_info = {
> @@ -448,6 +451,16 @@ static const struct ad4080_chip_info ad4080_chip_info = {
>  	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
>  };
>  
> +static const struct ad4080_chip_info ad4081_chip_info = {
> +	.name = "ad4081",
> +	.product_id = AD4081_CHIP_ID,
> +	.scale_table = ad4080_scale_table,
> +	.num_scales = ARRAY_SIZE(ad4080_scale_table),
> +	.num_channels = 1,
> +	.channels = &ad4081_channel,
> +	.lvds_cnv_clk_cnt_max = 2,
> +};
> +
>  static const struct ad4080_chip_info ad4084_chip_info = {
>  	.name = "ad4084",
>  	.product_id = AD4084_CHIP_ID,
> @@ -611,6 +624,7 @@ static int ad4080_probe(struct spi_device *spi)
>  
>  static const struct spi_device_id ad4080_id[] = {
>  	{ "ad4080", (kernel_ulong_t)&ad4080_chip_info },
> +	{ "ad4081", (kernel_ulong_t)&ad4081_chip_info },
>  	{ "ad4084", (kernel_ulong_t)&ad4084_chip_info },
>  	{ }
>  };
> @@ -618,6 +632,7 @@ MODULE_DEVICE_TABLE(spi, ad4080_id);
>  
>  static const struct of_device_id ad4080_of_match[] = {
>  	{ .compatible = "adi,ad4080", &ad4080_chip_info },
> +	{ .compatible = "adi,ad4081", &ad4081_chip_info },
>  	{ .compatible = "adi,ad4084", &ad4084_chip_info },
>  	{ }
>  };

Re: [PATCH v2 5/6] dt-bindings: iio: adc: adi,ad4080: add support for AD4081

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH v2 3/6] dt-bindings: iio: adc: adi,ad4080: add support for AD4084

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH v2 1/6] iio: adc: ad4080: fix chip identification

[Jonathan Cameron]

On Tue, 30 Sep 2025 13:35:46 +0100
Nuno Sá <noname.nuno@gmail.com> wrote:

> Hi Antoniu,
> 
> I think that for a series like this you should include a cover letter...
Yup. Then I'd be replying to that rather than here!

> 
> On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote:
> > Fix AD4080 chip identification by using the correct 16-bit product ID
> > (0x0050) instead of GENMASK(2, 0). Update the chip reading logic to
> > use regmap_bulk_read to read both PRODUCT_ID_L and PRODUCT_ID_H
> > registers and combine them into a 16-bit value.
> > 
> > The original implementation was incorrectly reading only 3 bits,
> > which would not correctly identify the AD4080 chip.
> > 
> > Fixes: 6b31ba1811b6 ("iio: adc: ad4080: add driver support")
> > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> > ---
> > changes in v2:
> >  - add the chip id handling into a separate commit.
> >  - use regmap_bulk_read.
> >  drivers/iio/adc/ad4080.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> > index 6e61787ed321..b80560aebe2d 100644
> > --- a/drivers/iio/adc/ad4080.c
> > +++ b/drivers/iio/adc/ad4080.c
> > @@ -125,7 +125,7 @@
> >  
> >  /* Miscellaneous Definitions */
> >  #define
> > AD4080_SPI_READ						BIT(7)
> > -#define AD4080_CHIP_ID						GENMASK(2, 0)
> > +#define AD4080_CHIP_ID						0x0050
> >  
> >  #define AD4080_LVDS_CNV_CLK_CNT_MAX				7
> >  
> > @@ -458,10 +458,11 @@ static int ad4080_setup(struct iio_dev *indio_dev)
> >  	if (ret)
> >  		return ret;
> >  
> > -	ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id);
> > +	ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id, 2);
> >  	if (ret)
> >  		return ret;
> >  
> > +	id = get_unaligned_le16(&id);  
> 
> Being id an 'unsigned int' I'm not really sure the above will work on big endian
> machines as we should only populate the 2 MSB, right? But independent of that,
> id is only being used in here so I would use proper __le16 (and u16) and
> le16_to_cpu().
> 
Spot on.  Types are a mess here and will trigger issues if sparse is pointed
at this code (and possibly other compiler related warnings).

The series otherwise looks good to me. You could probably have added all the DT
changes in one patch and all the devices support in another (rather than 2 of each)
but that's not important enough to change now.

So I'll pick the whole thing up on v3 once this type issue is resolved.

thanks,

Jonathan

> - Nuno Sá
> 
> >  	if (id != AD4080_CHIP_ID)
> >  		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
> >