* [PATCH 0/2] arm64: dts/thermal: Add MT8189 thermal controller and driver support @ 2025-11-10 9:40 Hanchien Lin 2025-11-10 9:40 ` [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node Hanchien Lin 2025-11-10 9:40 ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support Hanchien Lin 0 siblings, 2 replies; 6+ messages in thread From: Hanchien Lin @ 2025-11-10 9:40 UTC (permalink / raw) To: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, hanchien.lin, Project_Global_Chrome_Upstream_Group, raymond.sun, Irving-CH.lin This patch series adds support for the thermal controller on MediaTek MT8189 SoC. Patch 1 adds the device tree node for the MT8189 thermal controller. Patch 2 adds MT8189 support to the LVTS thermal driver. Hanchien Lin (2): arm64: dts: mediatek: mt8189: Add thermal controller node thermal/drivers/mediatek/lvts_thermal: Add MT8189 support .../thermal/mediatek,lvts-thermal.yaml | 27 ++- drivers/thermal/mediatek/lvts_thermal.c | 155 ++++++++++++++++-- .../thermal/mediatek,lvts-thermal.h | 20 +++ 3 files changed, 189 insertions(+), 13 deletions(-) -- 2.45.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node 2025-11-10 9:40 [PATCH 0/2] arm64: dts/thermal: Add MT8189 thermal controller and driver support Hanchien Lin @ 2025-11-10 9:40 ` Hanchien Lin 2025-11-10 18:45 ` Conor Dooley 2025-11-10 9:40 ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support Hanchien Lin 1 sibling, 1 reply; 6+ messages in thread From: Hanchien Lin @ 2025-11-10 9:40 UTC (permalink / raw) To: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, hanchien.lin, Project_Global_Chrome_Upstream_Group, raymond.sun, Irving-CH.lin Add device tree node for the thermal controller on MediaTek MT8189 SoC. Signed-off-by: Hanchien Lin <hanchien.lin@mediatek.com> --- .../thermal/mediatek,lvts-thermal.yaml | 27 +++++++++++++++++-- .../thermal/mediatek,lvts-thermal.h | 20 ++++++++++++++ 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml index 0259cd3ce9c5..0f7fd69f5fdf 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -22,6 +22,8 @@ properties: - mediatek,mt8186-lvts - mediatek,mt8188-lvts-ap - mediatek,mt8188-lvts-mcu + - mediatek,mt8189-lvts-ap + - mediatek,mt8189-lvts-mcu - mediatek,mt8192-lvts-ap - mediatek,mt8192-lvts-mcu - mediatek,mt8195-lvts-ap @@ -58,6 +60,21 @@ properties: allOf: - $ref: thermal-sensor.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8189-lvts-ap + - mediatek,mt8189-lvts-mcu + then: + properties: + nvmem-cells: + minItems: 2 + + nvmem-cell-names: + minItems: 2 + - if: properties: compatible: @@ -75,6 +92,10 @@ allOf: nvmem-cell-names: maxItems: 1 + required: + - clocks + - resets + - if: properties: compatible: @@ -91,12 +112,14 @@ allOf: nvmem-cell-names: minItems: 2 + required: + - clocks + - resets + required: - compatible - reg - interrupts - - clocks - - resets - nvmem-cells - nvmem-cell-names diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h index ddc7302a510a..6c9103dfdc2d 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -42,6 +42,26 @@ #define MT8188_AP_CAM1 6 #define MT8188_AP_CAM2 7 +#define MT8189_MCU_BIG_CPU1 0 +#define MT8189_MCU_BIG_CPU2 1 +#define MT8189_MCU_BIG_CPU3 2 +#define MT8189_MCU_BIG_CPU4 3 +#define MT8189_MCU_LITTLE_CPU1 4 +#define MT8189_MCU_LITTLE_CPU2 5 +#define MT8189_MCU_LITTLE_CPU3 6 +#define MT8189_MCU_LITTLE_CPU4 7 +#define MT8189_MCU_LITTLE_CPU5 8 +#define MT8189_MCU_LITTLE_CPU6 9 +#define MT8189_MCU_LITTLE_CPU7 10 +#define MT8189_MCU_LITTLE_CPU8 11 + +#define MT8189_AP_SOC1 12 +#define MT8189_AP_SOC2 13 +#define MT8189_AP_SOC3 14 +#define MT8189_AP_APU 15 +#define MT8189_AP_GPU1 16 +#define MT8189_AP_GPU2 17 + #define MT8195_MCU_BIG_CPU0 0 #define MT8195_MCU_BIG_CPU1 1 #define MT8195_MCU_BIG_CPU2 2 -- 2.45.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node 2025-11-10 9:40 ` [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node Hanchien Lin @ 2025-11-10 18:45 ` Conor Dooley 2025-12-02 8:02 ` Hanchien Lin (林翰謙) 0 siblings, 1 reply; 6+ messages in thread From: Conor Dooley @ 2025-11-10 18:45 UTC (permalink / raw) To: Hanchien Lin Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI, linux-pm, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, raymond.sun, Irving-CH.lin [-- Attachment #1: Type: text/plain, Size: 3381 bytes --] On Mon, Nov 10, 2025 at 05:40:38PM +0800, Hanchien Lin wrote: > Add device tree node for the thermal controller on MediaTek MT8189 SoC. $subject is incorrect for a binding change. pw-bot: changes-requested > > Signed-off-by: Hanchien Lin <hanchien.lin@mediatek.com> > --- > .../thermal/mediatek,lvts-thermal.yaml | 27 +++++++++++++++++-- > .../thermal/mediatek,lvts-thermal.h | 20 ++++++++++++++ > 2 files changed, 45 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > index 0259cd3ce9c5..0f7fd69f5fdf 100644 > --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > @@ -22,6 +22,8 @@ properties: > - mediatek,mt8186-lvts > - mediatek,mt8188-lvts-ap > - mediatek,mt8188-lvts-mcu > + - mediatek,mt8189-lvts-ap > + - mediatek,mt8189-lvts-mcu > - mediatek,mt8192-lvts-ap > - mediatek,mt8192-lvts-mcu > - mediatek,mt8195-lvts-ap > @@ -58,6 +60,21 @@ properties: > allOf: > - $ref: thermal-sensor.yaml# > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8189-lvts-ap > + - mediatek,mt8189-lvts-mcu > + then: > + properties: > + nvmem-cells: > + minItems: 2 > + > + nvmem-cell-names: > + minItems: 2 > + > - if: > properties: > compatible: > @@ -75,6 +92,10 @@ allOf: > nvmem-cell-names: > maxItems: 1 > > + required: > + - clocks > + - resets > + > - if: > properties: > compatible: > @@ -91,12 +112,14 @@ allOf: > nvmem-cell-names: > minItems: 2 > > + required: > + - clocks > + - resets > + > required: > - compatible > - reg > - interrupts > - - clocks > - - resets > - nvmem-cells > - nvmem-cell-names > > diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > index ddc7302a510a..6c9103dfdc2d 100644 > --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h > +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > @@ -42,6 +42,26 @@ > #define MT8188_AP_CAM1 6 > #define MT8188_AP_CAM2 7 > > +#define MT8189_MCU_BIG_CPU1 0 > +#define MT8189_MCU_BIG_CPU2 1 > +#define MT8189_MCU_BIG_CPU3 2 > +#define MT8189_MCU_BIG_CPU4 3 > +#define MT8189_MCU_LITTLE_CPU1 4 > +#define MT8189_MCU_LITTLE_CPU2 5 > +#define MT8189_MCU_LITTLE_CPU3 6 > +#define MT8189_MCU_LITTLE_CPU4 7 > +#define MT8189_MCU_LITTLE_CPU5 8 > +#define MT8189_MCU_LITTLE_CPU6 9 > +#define MT8189_MCU_LITTLE_CPU7 10 > +#define MT8189_MCU_LITTLE_CPU8 11 > + > +#define MT8189_AP_SOC1 12 > +#define MT8189_AP_SOC2 13 > +#define MT8189_AP_SOC3 14 > +#define MT8189_AP_APU 15 > +#define MT8189_AP_GPU1 16 > +#define MT8189_AP_GPU2 17 > + > #define MT8195_MCU_BIG_CPU0 0 > #define MT8195_MCU_BIG_CPU1 1 > #define MT8195_MCU_BIG_CPU2 2 > -- > 2.45.2 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node 2025-11-10 18:45 ` Conor Dooley @ 2025-12-02 8:02 ` Hanchien Lin (林翰謙) 0 siblings, 0 replies; 6+ messages in thread From: Hanchien Lin (林翰謙) @ 2025-12-02 8:02 UTC (permalink / raw) To: Conor Dooley Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group, Raymond Sun (孫俊斌), Irving-CH Lin (林建弘) Hi Conor, Thanks for your feedback. Sorry for overlooking this part. I will update the patch subject and include the missing content in v3. Best regards, Hanchien Lin. -----Original Message----- From: Conor Dooley <conor@kernel.org> Sent: Tuesday, November 11, 2025 2:45 AM To: Hanchien Lin (林翰謙) <Hanchien.Lin@mediatek.com> Cc: Rafael J . Wysocki <rafael@kernel.org>; Daniel Lezcano <daniel.lezcano@linaro.org>; Zhang Rui <rui.zhang@intel.com>; Lukasz Luba <lukasz.luba@arm.com>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Philipp Zabel <p.zabel@pengutronix.de>; Matthias Brugger <matthias.bgg@gmail.com>; AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>; Balsam CHIHI <bchihi@baylibre.com>; linux-pm@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-mediatek@lists.infradead.org; Project_Global_Chrome_Upstream_Group <Project_Global_Chrome_Upstream_Group@mediatek.com>; Raymond Sun (孫俊斌) <Raymond.Sun@mediatek.com>; Irving-CH Lin (林建弘) <Irving-CH.Lin@mediatek.com> Subject: Re: [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node On Mon, Nov 10, 2025 at 05:40:38PM +0800, Hanchien Lin wrote: > Add device tree node for the thermal controller on MediaTek MT8189 SoC. $subject is incorrect for a binding change. pw-bot: changes-requested > > Signed-off-by: Hanchien Lin <hanchien.lin@mediatek.com> > --- > .../thermal/mediatek,lvts-thermal.yaml | 27 +++++++++++++++++-- > .../thermal/mediatek,lvts-thermal.h | 20 ++++++++++++++ > 2 files changed, 45 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > index 0259cd3ce9c5..0f7fd69f5fdf 100644 > --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml > @@ -22,6 +22,8 @@ properties: > - mediatek,mt8186-lvts > - mediatek,mt8188-lvts-ap > - mediatek,mt8188-lvts-mcu > + - mediatek,mt8189-lvts-ap > + - mediatek,mt8189-lvts-mcu > - mediatek,mt8192-lvts-ap > - mediatek,mt8192-lvts-mcu > - mediatek,mt8195-lvts-ap > @@ -58,6 +60,21 @@ properties: > allOf: > - $ref: thermal-sensor.yaml# > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8189-lvts-ap > + - mediatek,mt8189-lvts-mcu > + then: > + properties: > + nvmem-cells: > + minItems: 2 > + > + nvmem-cell-names: > + minItems: 2 > + > - if: > properties: > compatible: > @@ -75,6 +92,10 @@ allOf: > nvmem-cell-names: > maxItems: 1 > > + required: > + - clocks > + - resets > + > - if: > properties: > compatible: > @@ -91,12 +112,14 @@ allOf: > nvmem-cell-names: > minItems: 2 > > + required: > + - clocks > + - resets > + > required: > - compatible > - reg > - interrupts > - - clocks > - - resets > - nvmem-cells > - nvmem-cell-names > > diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > index ddc7302a510a..6c9103dfdc2d 100644 > --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h > +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > @@ -42,6 +42,26 @@ > #define MT8188_AP_CAM1 6 > #define MT8188_AP_CAM2 7 > > +#define MT8189_MCU_BIG_CPU1 0 > +#define MT8189_MCU_BIG_CPU2 1 > +#define MT8189_MCU_BIG_CPU3 2 > +#define MT8189_MCU_BIG_CPU4 3 > +#define MT8189_MCU_LITTLE_CPU1 4 > +#define MT8189_MCU_LITTLE_CPU2 5 > +#define MT8189_MCU_LITTLE_CPU3 6 > +#define MT8189_MCU_LITTLE_CPU4 7 > +#define MT8189_MCU_LITTLE_CPU5 8 > +#define MT8189_MCU_LITTLE_CPU6 9 > +#define MT8189_MCU_LITTLE_CPU7 10 > +#define MT8189_MCU_LITTLE_CPU8 11 > + > +#define MT8189_AP_SOC1 12 > +#define MT8189_AP_SOC2 13 > +#define MT8189_AP_SOC3 14 > +#define MT8189_AP_APU 15 > +#define MT8189_AP_GPU1 16 > +#define MT8189_AP_GPU2 17 > + > #define MT8195_MCU_BIG_CPU0 0 > #define MT8195_MCU_BIG_CPU1 1 > #define MT8195_MCU_BIG_CPU2 2 > -- > 2.45.2 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support 2025-11-10 9:40 [PATCH 0/2] arm64: dts/thermal: Add MT8189 thermal controller and driver support Hanchien Lin 2025-11-10 9:40 ` [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node Hanchien Lin @ 2025-11-10 9:40 ` Hanchien Lin 2025-11-10 9:53 ` Philipp Zabel 1 sibling, 1 reply; 6+ messages in thread From: Hanchien Lin @ 2025-11-10 9:40 UTC (permalink / raw) To: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, hanchien.lin, Project_Global_Chrome_Upstream_Group, raymond.sun, Irving-CH.lin Add support for the MediaTek MT8189 SoC to the LVTS thermal driver. Signed-off-by: Hanchien Lin <hanchien.lin@mediatek.com> --- drivers/thermal/mediatek/lvts_thermal.c | 155 ++++++++++++++++++++++-- 1 file changed, 144 insertions(+), 11 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index ab55b20cda47..8c15fdaac48c 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -65,6 +65,7 @@ #define LVTS_HW_FILTER 0x0 #define LVTS_TSSEL_CONF 0x13121110 #define LVTS_CALSCALE_CONF 0x300 +#define LVTS_MONINT_CONF_STAGE3 BIT(31) #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3) #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8) @@ -107,6 +108,7 @@ struct lvts_sensor_data { struct lvts_ctrl_data { struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; u8 valid_sensor_mask; + int hw_tshut_temp; int offset; int mode; }; @@ -134,6 +136,9 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + bool clock_gate_no_need; + bool reset_no_need; + bool conf_stage3_need; }; struct lvts_sensor { @@ -150,6 +155,7 @@ struct lvts_ctrl { struct lvts_sensor sensors[LVTS_SENSOR_MAX]; const struct lvts_data *lvts_data; u32 calibration[LVTS_SENSOR_MAX]; + u32 hw_tshut_raw_temp; u8 valid_sensor_mask; int mode; void __iomem *base; @@ -859,6 +865,14 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, */ lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; + /* + * The temperature to raw temperature must be done + * after initializing the calibration. + */ + lvts_ctrl[i].hw_tshut_raw_temp = + lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, + lvts_data->temp_factor); + lvts_ctrl[i].low_thresh = INT_MIN; lvts_ctrl[i].high_thresh = INT_MIN; } @@ -919,7 +933,7 @@ static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int } } -static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) +static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl, const struct lvts_data *lvts_data) { /* * LVTS_PROTCTL : Thermal Protection Sensor Selection @@ -947,6 +961,7 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); * writel(0x0, LVTS_PROTTC(lvts_ctrl->base)); */ + writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); /* * LVTS_MONINT : Interrupt configuration register @@ -954,7 +969,10 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS * register, except we set the bits to enable the interrupt. */ - writel(0, LVTS_MONINT(lvts_ctrl->base)); + if (lvts_data->conf_stage3_need) + writel(LVTS_MONINT_CONF_STAGE3, LVTS_MONINT(lvts_ctrl->base)); + else + writel(0, LVTS_MONINT(lvts_ctrl->base)); return 0; } @@ -1041,7 +1059,8 @@ static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) return 0; } -static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl, + const struct lvts_data *lvts_data) { u32 value; @@ -1143,7 +1162,7 @@ static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; writel(value, LVTS_MONCTL2(lvts_ctrl->base)); - return lvts_irq_init(lvts_ctrl); + return lvts_irq_init(lvts_ctrl, lvts_data); } static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) @@ -1290,7 +1309,7 @@ static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, return ret; } - ret = lvts_ctrl_configure(dev, lvts_ctrl); + ret = lvts_ctrl_configure(dev, lvts_ctrl, lvts_data); if (ret) { dev_dbg(dev, "Failed to configure controller"); return ret; @@ -1322,9 +1341,15 @@ static int lvts_probe(struct platform_device *pdev) if (!lvts_data) return -ENODEV; - lvts_td->clk = devm_clk_get_enabled(dev, NULL); - if (IS_ERR(lvts_td->clk)) - return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); + if (!lvts_data->clock_gate_no_need) { + lvts_td->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(lvts_td->clk)) + return dev_err_probe( + dev, + PTR_ERR(lvts_td->clk), + "Failed to retrieve clock\n" + ); + } res = platform_get_mem_or_io(pdev, 0); if (!res) @@ -1334,9 +1359,15 @@ static int lvts_probe(struct platform_device *pdev) if (IS_ERR(lvts_td->base)) return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); - lvts_td->reset = devm_reset_control_get_by_index(dev, 0); - if (IS_ERR(lvts_td->reset)) - return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); + if (!lvts_data->reset_no_need) { + lvts_td->reset = devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_td->reset)) + return dev_err_probe( + dev, + PTR_ERR(lvts_td->reset), + "Failed to get reset control\n" + ); + } irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -1586,6 +1617,78 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { } }; +static const struct lvts_ctrl_data mt8189_lvts_mcu_data_ctrl[] = { + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_LITTLE_CPU1, + .cal_offsets = { 4, 5, 6 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU2, + .cal_offsets = { 8, 9, 10 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU3, + .cal_offsets = { 12, 13, 14 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU4, + .cal_offsets = { 16, 17, 18 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x0, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_LITTLE_CPU5, + .cal_offsets = { 24, 25, 26 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU6, + .cal_offsets = { 28, 29, 30 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU7, + .cal_offsets = { 32, 33, 34 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU8, + .cal_offsets = { 36, 37, 38 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x100, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_BIG_CPU1, + .cal_offsets = { 44, 45, 46 } }, + { .dt_id = MT8189_MCU_BIG_CPU2, + .cal_offsets = { 48, 49, 50 } }, + { .dt_id = MT8189_MCU_BIG_CPU3, + .cal_offsets = { 52, 53, 54 } }, + { .dt_id = MT8189_MCU_BIG_CPU4, + .cal_offsets = { 56, 57, 58 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x200, + } +}; + +static const struct lvts_ctrl_data mt8189_lvts_ap_data_ctrl[] = { + { + .lvts_sensor = { + { .dt_id = MT8189_AP_SOC1, + .cal_offsets = { 64, 65, 66 } }, + { .dt_id = MT8189_AP_SOC2, + .cal_offsets = { 68, 69, 70 } }, + { .dt_id = MT8189_AP_SOC3, + .cal_offsets = { 72, 73, 74 } }, + { .dt_id = MT8189_AP_APU, + .cal_offsets = { 76, 77, 78 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x0, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_AP_GPU1, + .cal_offsets = { 84, 85, 86 } }, + { .dt_id = MT8189_AP_GPU2, + .cal_offsets = { 88, 89, 90 } } + }, + VALID_SENSOR_MAP(1, 1, 0, 0), + .offset = 0x100, + } +}; + static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { { .lvts_sensor = { @@ -1804,6 +1907,34 @@ static const struct lvts_data mt8188_lvts_ap_data = { .def_calibration = 35000, }; +static const struct lvts_data mt8189_lvts_ap_data = { + .lvts_ctrl = mt8189_lvts_ap_data_ctrl, + .conn_cmd = default_conn_cmds, + .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8189_lvts_ap_data_ctrl), + .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), + .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 0, + .def_calibration = 35000, + .clock_gate_no_need = true, + .reset_no_need = true, + .conf_stage3_need = true, +}; + +static const struct lvts_data mt8189_lvts_mcu_data = { + .lvts_ctrl = mt8189_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8189_lvts_mcu_data_ctrl), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 0, + .def_calibration = 35000, + .clock_gate_no_need = true, + .reset_no_need = true, + .conf_stage3_need = true, +}; + static const struct lvts_data mt8192_lvts_mcu_data = { .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, .conn_cmd = default_conn_cmds, @@ -1861,6 +1992,8 @@ static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, + { .compatible = "mediatek,mt8189-lvts-mcu", .data = &mt8189_lvts_mcu_data }, + { .compatible = "mediatek,mt8189-lvts-ap", .data = &mt8189_lvts_ap_data }, { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, -- 2.45.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support 2025-11-10 9:40 ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support Hanchien Lin @ 2025-11-10 9:53 ` Philipp Zabel 0 siblings, 0 replies; 6+ messages in thread From: Philipp Zabel @ 2025-11-10 9:53 UTC (permalink / raw) To: Hanchien Lin, Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Balsam CHIHI Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, raymond.sun, Irving-CH.lin On Mo, 2025-11-10 at 17:40 +0800, Hanchien Lin wrote: > Add support for the MediaTek MT8189 SoC to the LVTS thermal driver. > > Signed-off-by: Hanchien Lin <hanchien.lin@mediatek.com> > --- > drivers/thermal/mediatek/lvts_thermal.c | 155 ++++++++++++++++++++++-- > 1 file changed, 144 insertions(+), 11 deletions(-) > > diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c > index ab55b20cda47..8c15fdaac48c 100644 > --- a/drivers/thermal/mediatek/lvts_thermal.c > +++ b/drivers/thermal/mediatek/lvts_thermal.c [...] > @@ -1334,9 +1359,15 @@ static int lvts_probe(struct platform_device *pdev) > if (IS_ERR(lvts_td->base)) > return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); > > - lvts_td->reset = devm_reset_control_get_by_index(dev, 0); > - if (IS_ERR(lvts_td->reset)) > - return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); > + if (!lvts_data->reset_no_need) { > + lvts_td->reset = devm_reset_control_get_by_index(dev, 0); This should be devm_reset_control_get_exclusive(dev, NULL) instead of devm_reset_control_get_by_index(dev, 0). No need to use by_index for a single reset control. regards Philipp ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-12-02 8:02 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-10 9:40 [PATCH 0/2] arm64: dts/thermal: Add MT8189 thermal controller and driver support Hanchien Lin 2025-11-10 9:40 ` [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node Hanchien Lin 2025-11-10 18:45 ` Conor Dooley 2025-12-02 8:02 ` Hanchien Lin (林翰謙) 2025-11-10 9:40 ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support Hanchien Lin 2025-11-10 9:53 ` Philipp Zabel
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