From: Dong Aisheng <aisheng.dong@nxp.com>
To: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
kernel@pengutronix.de, dongas86@gmail.com, krzk+dt@kernel.org,
robh@kernel.org, shawnguo@kernel.org, frank.li@nxp.com,
kernel@dh-electronics.com, linux@ew.tq-group.com,
francesco.dolcini@toradex.com, Anson Huang <Anson.Huang@nxp.com>,
Dong Aisheng <aisheng.dong@nxp.com>
Subject: [PATCH 1/1] arm64: dts: imx8mp: Update pin function file according to Rev.D RM
Date: Mon, 24 Nov 2025 17:54:49 +0800 [thread overview]
Message-ID: <20251124095449.4027676-1-aisheng.dong@nxp.com> (raw)
From: Anson Huang <Anson.Huang@nxp.com>
Update i.MX8MP imx8mp-pinfunc.h file according to reference manual Rev.D.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
NOTE: I met the following checkpatch error, could you advise how to
handle it?
ERROR: Macros with complex values should be enclosed in parentheses
+#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0
---
.../dts/freescale/imx8mp-data-modul-edm-sbc.dts | 4 ++--
.../boot/dts/freescale/imx8mp-debix-model-a.dts | 2 +-
.../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 4 ++--
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
.../boot/dts/freescale/imx8mp-iota2-lumpy.dts | 2 +-
.../boot/dts/freescale/imx8mp-kontron-osm-s.dtsi | 6 +++---
.../imx8mp-nitrogen-enc-carrier-board.dts | 2 +-
.../boot/dts/freescale/imx8mp-phycore-fpsc.dtsi | 12 ++++++------
arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 16 ++++++++--------
.../dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 4 ++--
.../boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 2 +-
.../boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +-
.../boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +-
.../boot/dts/freescale/imx8mp-venice-gw74xx.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 2 +-
15 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
index 16078ff60ef08..7a05e0692d78d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
@@ -1085,8 +1085,8 @@ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4
pinctrl_usb1: usb1-grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
+ MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x6
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x80
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
index 9422beee30b29..2df6434bde652 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
@@ -485,7 +485,7 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x10
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
index 68c2e0156a5c8..755ea967bb9cb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
@@ -1061,8 +1061,8 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
pinctrl_usb1_vbus: dhcom-usb1-grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
- MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x6
+ MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x80
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index c6facb2ad9aaa..57accd33ec62c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -1088,7 +1088,7 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x19
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts b/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts
index f48cf22b423db..f66c6b9236fbe 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts
@@ -363,7 +363,7 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0
pinctrl_usb_host_vbus: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x0
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x0
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
index b97bfeb1c30f8..6de4d4ace8a73 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
@@ -734,19 +734,19 @@ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4 /* USB_A_ID */
pinctrl_usb1_oc: usb1ocgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0 /* USB_A_OC# */
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c0 /* USB_A_OC# */
>;
};
pinctrl_usb2_id: usb2idgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x1c4 /* USB_B_ID */
+ MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x1c4 /* USB_B_ID */
>;
};
pinctrl_usb2_oc: usb2ocgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0 /* USB_B_OC# */
+ MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x1c0 /* USB_B_OC# */
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts
index 1df9488aaeb22..9ffeeb382bad4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts
@@ -406,7 +406,7 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c0
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi
index 8b0e8cf86cadb..7b5c402ff9f27 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi
@@ -579,17 +579,17 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART3_TXD */
pinctrl_usb0: usb0grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x106 /* USB1_PWR_EN */
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x106 /* USB1_OC */
- MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x106 /* USB1_ID */
+ MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x106 /* USB1_PWR_EN */
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x106 /* USB1_OC */
+ MX8MP_IOMUXC_GPIO1_IO10__USB1_ID 0x106 /* USB1_ID */
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x106 /* USB2_PWR_EN */
- MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x106 /* USB2_OC */
- MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x106 /* USB2_ID */
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x106 /* USB2_PWR_EN */
+ MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x106 /* USB2_OC */
+ MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x106 /* USB2_ID */
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
index 16f5899de4152..50f5e674a6b71 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
@@ -46,10 +46,12 @@
#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
+#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
+#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
@@ -91,26 +93,26 @@
#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO10__USB1_ID 0x03C 0x29C 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x040 0x2A0 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1
#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x044 0x2A4 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x048 0x2A8 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x04C 0x2AC 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0
-#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0
+#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x050 0x2B0 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0
@@ -291,10 +293,8 @@
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2
#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0
-#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0
#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0
-#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0
#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index 59642a8a2c445..50c8a7c2a7bd3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -976,8 +976,8 @@ pinctrl_uart4: uart4grp {
};
pinctrl_usb0: usb0grp {
- fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>,
- <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>;
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c0>,
+ <MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x1c0>;
};
pinctrl_usbcon0: usb0congrp {
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
index 4bf818873fe3c..162329b403d30 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
@@ -219,7 +219,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x140 /* USB1_FLT# */
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
index 76020ef89bf3e..02ea0e8bcc6ff 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -318,7 +318,7 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x140 /* USB1_FLT# */
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
index 5eb114d2360a3..2b6bb9fcbc7a9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
@@ -359,7 +359,7 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x140 /* USB1_FLT# */
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index 7662663ff5dad..6d752fe0d1bf5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -1060,7 +1060,7 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
pinctrl_usb1: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
+ MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x140
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index d43ba00871269..28f5983a78469 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -1316,7 +1316,7 @@ pinctrl_usb_1_id: usb1idgrp {
/* USB_1_OC# */
pinctrl_usb_1_oc_n: usb1ocngrp {
fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
+ <MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c4>; /* SODIMM 157 */
};
pinctrl_usb2_vbus: usb2vbusgrp {
--
2.37.1
next reply other threads:[~2025-11-24 9:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 9:54 Dong Aisheng [this message]
2025-11-24 11:11 ` [PATCH 1/1] arm64: dts: imx8mp: Update pin function file according to Rev.D RM Alexander Stein
2025-11-24 13:46 ` Aisheng Dong
2025-11-24 13:56 ` Alexander Stein
2025-11-24 12:07 ` Ahmad Fatoum
2025-11-24 13:39 ` Aisheng Dong
2025-11-24 13:54 ` Ahmad Fatoum
2025-11-24 15:08 ` Aisheng Dong
2025-11-24 15:19 ` Ahmad Fatoum
2025-11-25 0:15 ` Andrew Lunn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251124095449.4027676-1-aisheng.dong@nxp.com \
--to=aisheng.dong@nxp.com \
--cc=Anson.Huang@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=dongas86@gmail.com \
--cc=francesco.dolcini@toradex.com \
--cc=frank.li@nxp.com \
--cc=imx@lists.linux.dev \
--cc=kernel@dh-electronics.com \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux@ew.tq-group.com \
--cc=robh@kernel.org \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox