* [PATCH v2 0/9] Add RZ/G3L IRQC support
@ 2026-02-04 18:06 Biju
2026-02-04 18:06 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Biju
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Biju @ 2026-02-04 18:06 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
The IRQC block on RZ/G3L SoC is almost identical to one found on the
RZ/G3S SoC with the difference like it support more External IRQs, GPT
Error Interrupts and also has additional registers for GPT/MTU IRQ
selection, shared IRQ selection between external IRQ and TINT.
It has 16 external interrupts of which 8 interrupts are shared with
TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
selection is based on a register in the ICU block.
v1->v2:
* Simplified the binding by using pattern for intterrupt-names
* Fixed the binding warnings reported by bot.
Biju Das (9):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
interrupt-names
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
SoC
irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct
rzg2l_irqc_priv
irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
irqchip/renesas-rzg2l: Add RZ/G3L support
irqchip/renesas-rzg2l: Add shared irq support
arm64: dts: renesas: r9a08g046: Add ICU node
.../renesas,rzg2l-irqc.yaml | 156 +++++--------
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 91 ++++++++
drivers/irqchip/irq-renesas-rzg2l.c | 218 +++++++++++++++---
3 files changed, 336 insertions(+), 129 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names
2026-02-04 18:06 [PATCH v2 0/9] Add RZ/G3L IRQC support Biju
@ 2026-02-04 18:06 ` Biju
2026-02-10 1:14 ` Rob Herring (Arm)
2026-02-04 18:06 ` [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Biju
2026-02-04 18:06 ` [PATCH v2 9/9] arm64: dts: renesas: r9a08g046: Add ICU node Biju
2 siblings, 1 reply; 7+ messages in thread
From: Biju @ 2026-02-04 18:06 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Simplify the bindings by using pattern property for interrupt-names.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* New patch.
---
.../renesas,rzg2l-irqc.yaml | 120 ++++--------------
1 file changed, 23 insertions(+), 97 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 44b6ae5fc802..a0b57d808639 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -48,107 +48,33 @@ properties:
interrupts:
minItems: 45
- items:
- - description: NMI interrupt
- - description: IRQ0 interrupt
- - description: IRQ1 interrupt
- - description: IRQ2 interrupt
- - description: IRQ3 interrupt
- - description: IRQ4 interrupt
- - description: IRQ5 interrupt
- - description: IRQ6 interrupt
- - description: IRQ7 interrupt
- - description: GPIO interrupt, TINT0
- - description: GPIO interrupt, TINT1
- - description: GPIO interrupt, TINT2
- - description: GPIO interrupt, TINT3
- - description: GPIO interrupt, TINT4
- - description: GPIO interrupt, TINT5
- - description: GPIO interrupt, TINT6
- - description: GPIO interrupt, TINT7
- - description: GPIO interrupt, TINT8
- - description: GPIO interrupt, TINT9
- - description: GPIO interrupt, TINT10
- - description: GPIO interrupt, TINT11
- - description: GPIO interrupt, TINT12
- - description: GPIO interrupt, TINT13
- - description: GPIO interrupt, TINT14
- - description: GPIO interrupt, TINT15
- - description: GPIO interrupt, TINT16
- - description: GPIO interrupt, TINT17
- - description: GPIO interrupt, TINT18
- - description: GPIO interrupt, TINT19
- - description: GPIO interrupt, TINT20
- - description: GPIO interrupt, TINT21
- - description: GPIO interrupt, TINT22
- - description: GPIO interrupt, TINT23
- - description: GPIO interrupt, TINT24
- - description: GPIO interrupt, TINT25
- - description: GPIO interrupt, TINT26
- - description: GPIO interrupt, TINT27
- - description: GPIO interrupt, TINT28
- - description: GPIO interrupt, TINT29
- - description: GPIO interrupt, TINT30
- - description: GPIO interrupt, TINT31
- - description: Bus error interrupt
- - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
- - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
- - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
- - description: ECCRAM1 1bit error interrupt
- - description: ECCRAM1 2bit error interrupt
- - description: ECCRAM1 error overflow interrupt
+ maxItems: 48
interrupt-names:
minItems: 45
+ maxItems: 48
items:
- - const: nmi
- - const: irq0
- - const: irq1
- - const: irq2
- - const: irq3
- - const: irq4
- - const: irq5
- - const: irq6
- - const: irq7
- - const: tint0
- - const: tint1
- - const: tint2
- - const: tint3
- - const: tint4
- - const: tint5
- - const: tint6
- - const: tint7
- - const: tint8
- - const: tint9
- - const: tint10
- - const: tint11
- - const: tint12
- - const: tint13
- - const: tint14
- - const: tint15
- - const: tint16
- - const: tint17
- - const: tint18
- - const: tint19
- - const: tint20
- - const: tint21
- - const: tint22
- - const: tint23
- - const: tint24
- - const: tint25
- - const: tint26
- - const: tint27
- - const: tint28
- - const: tint29
- - const: tint30
- - const: tint31
- - const: bus-err
- - const: ec7tie1-0
- - const: ec7tie2-0
- - const: ec7tiovf-0
- - const: ec7tie1-1
- - const: ec7tie2-1
- - const: ec7tiovf-1
+ oneOf:
+ - description: NMI interrupt
+ const: nmi
+ - description: External IRQ interrupt
+ pattern: '^irq([0-7])$'
+ - description: GPIO interrupt
+ pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
+ - description: Bus error interrupt
+ const: bus-err
+ - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
+ const: ec7tie1-0
+ - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
+ const: ec7tie2-0
+ - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
+ const: ec7tiovf-0
+ - description: ECCRAM1 1bit error interrupt
+ const: ec7tie1-1
+ - description: ECCRAM1 2bit error interrupt
+ const: ec7tie2-1
+ - description: ECCRAM1 error overflow interrupt
+ const: ec7tiovf-1
clocks:
maxItems: 2
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
2026-02-04 18:06 [PATCH v2 0/9] Add RZ/G3L IRQC support Biju
2026-02-04 18:06 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Biju
@ 2026-02-04 18:06 ` Biju
2026-02-05 13:39 ` Krzysztof Kozlowski
2026-02-04 18:06 ` [PATCH v2 9/9] arm64: dts: renesas: r9a08g046: Add ICU node Biju
2 siblings, 1 reply; 7+ messages in thread
From: Biju @ 2026-02-04 18:06 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC
is almost identical to one found on the RZ/G3S SoC with the difference
like it support more External IRQs, GPT Error Interrupts and also has
additional registers for GPT/MTU IRQ selection, shared IRQ selection
between external IRQ and TINT. Hence new generic compatible string
"renesas,r9a08g046-irqc" is added for RZ/G3L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Simplified the binding using pattern
---
.../renesas,rzg2l-irqc.yaml | 42 +++++++++++++++----
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index a0b57d808639..311741122b05 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -30,7 +30,10 @@ properties:
- renesas,r9a08g045-irqc # RZ/G3S
- const: renesas,rzg2l-irqc
- - const: renesas,r9a07g043f-irqc # RZ/Five
+ - items:
+ - enum:
+ - renesas,r9a07g043f-irqc # RZ/Five
+ - renesas,r9a08g046-irqc # RZ/G3L
'#interrupt-cells':
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
@@ -48,17 +51,17 @@ properties:
interrupts:
minItems: 45
- maxItems: 48
+ maxItems: 61
interrupt-names:
minItems: 45
- maxItems: 48
+ maxItems: 61
items:
oneOf:
- description: NMI interrupt
const: nmi
- description: External IRQ interrupt
- pattern: '^irq([0-7])$'
+ pattern: '^irq([0-9]|1[0-5])$'
- description: GPIO interrupt
pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
- description: Bus error interrupt
@@ -75,6 +78,8 @@ properties:
const: ec7tie2-1
- description: ECCRAM1 error overflow interrupt
const: ec7tiovf-1
+ - description: Integrated GPT Error interrupt
+ pattern: '^ovfunf([0-7])$'
clocks:
maxItems: 2
@@ -106,6 +111,22 @@ required:
allOf:
- $ref: /schemas/interrupt-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a07g043f-irqc
+ - renesas,r9a07g043u-irqc
+ - renesas,r9a07g044-irqc
+ - renesas,r9a07g054-irqc
+ then:
+ properties:
+ interrupts:
+ maxItems: 48
+ interrupt-names:
+ maxItems: 48
+
- if:
properties:
compatible:
@@ -118,12 +139,19 @@ allOf:
maxItems: 45
interrupt-names:
maxItems: 45
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a08g046-irqc
+ then:
properties:
interrupts:
- minItems: 48
+ maxItems: 61
interrupt-names:
- minItems: 48
+ maxItems: 61
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 9/9] arm64: dts: renesas: r9a08g046: Add ICU node
2026-02-04 18:06 [PATCH v2 0/9] Add RZ/G3L IRQC support Biju
2026-02-04 18:06 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Biju
2026-02-04 18:06 ` [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Biju
@ 2026-02-04 18:06 ` Biju
2 siblings, 0 replies; 7+ messages in thread
From: Biju @ 2026-02-04 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI
and add icu as interrupt-parent of pincontrol.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
This patch depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20260203131048.421708-9-biju.das.jz@bp.renesas.com/T/#u
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index a92a4e07cc10..65dfa145ef59 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -188,6 +188,7 @@ pinctrl: pinctrl@11030000 {
gpio-ranges = <&pinctrl 0 0 232>;
interrupt-controller;
#interrupt-cells = <2>;
+ interrupt-parent = <&icu>;
clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A08G046_GPIO_RSTN>,
@@ -196,6 +197,96 @@ pinctrl: pinctrl@11030000 {
reset-names = "rstn", "port", "spare";
};
+ icu: interrupt-controller@11050000 {
+ compatible = "renesas,r9a08g046-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0",
+ "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3",
+ "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7";
+ clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>,
+ <&cpg CPG_MOD R9A08G046_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G046_IA55_RESETN>;
+ };
+
dmac: dma-controller@11820000 {
compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
2026-02-04 18:06 ` [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Biju
@ 2026-02-05 13:39 ` Krzysztof Kozlowski
2026-02-06 9:00 ` Biju Das
0 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2026-02-05 13:39 UTC (permalink / raw)
To: Biju
Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, Lad Prabhakar,
linux-kernel, devicetree, linux-renesas-soc
On Wed, Feb 04, 2026 at 06:06:18PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC
> is almost identical to one found on the RZ/G3S SoC with the difference
> like it support more External IRQs, GPT Error Interrupts and also has
> additional registers for GPT/MTU IRQ selection, shared IRQ selection
> between external IRQ and TINT. Hence new generic compatible string
> "renesas,r9a08g046-irqc" is added for RZ/G3L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Simplified the binding using pattern
> ---
> .../renesas,rzg2l-irqc.yaml | 42 +++++++++++++++----
> 1 file changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index a0b57d808639..311741122b05 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -30,7 +30,10 @@ properties:
> - renesas,r9a08g045-irqc # RZ/G3S
> - const: renesas,rzg2l-irqc
>
> - - const: renesas,r9a07g043f-irqc # RZ/Five
> + - items:
Drop items. The point was to simplify, so just enum.
> + - enum:
> + - renesas,r9a07g043f-irqc # RZ/Five
> + - renesas,r9a08g046-irqc # RZ/G3L
>
> '#interrupt-cells':
> description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
> @@ -48,17 +51,17 @@ properties:
>
> interrupts:
> minItems: 45
> - maxItems: 48
> + maxItems: 61
>
> interrupt-names:
> minItems: 45
> - maxItems: 48
> + maxItems: 61
> items:
> oneOf:
> - description: NMI interrupt
> const: nmi
> - description: External IRQ interrupt
> - pattern: '^irq([0-7])$'
> + pattern: '^irq([0-9]|1[0-5])$'
> - description: GPIO interrupt
> pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
> - description: Bus error interrupt
> @@ -75,6 +78,8 @@ properties:
> const: ec7tie2-1
> - description: ECCRAM1 error overflow interrupt
> const: ec7tiovf-1
> + - description: Integrated GPT Error interrupt
> + pattern: '^ovfunf([0-7])$'
>
> clocks:
> maxItems: 2
> @@ -106,6 +111,22 @@ required:
> allOf:
> - $ref: /schemas/interrupt-controller.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a07g043f-irqc
> + - renesas,r9a07g043u-irqc
> + - renesas,r9a07g044-irqc
> + - renesas,r9a07g054-irqc
> + then:
> + properties:
> + interrupts:
Missing minitems. Previously it was not 45, was it?
> + maxItems: 48
> + interrupt-names:
> + maxItems: 48
> +
> - if:
> properties:
> compatible:
> @@ -118,12 +139,19 @@ allOf:
> maxItems: 45
> interrupt-names:
> maxItems: 45
> - else:
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a08g046-irqc
> + then:
> properties:
> interrupts:
> - minItems: 48
> + maxItems: 61
minItems instead. Just like it was in the old code.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
2026-02-05 13:39 ` Krzysztof Kozlowski
@ 2026-02-06 9:00 ` Biju Das
0 siblings, 0 replies; 7+ messages in thread
From: Biju Das @ 2026-02-06 9:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, biju.das.au
Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Prabhakar Mahadev Lad,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Krzysztof Kozlowski,
Thanks for the feedback.
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 05 February 2026 13:39
> Subject: Re: [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
>
> On Wed, Feb 04, 2026 at 06:06:18PM +0000, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L
> > SoC is almost identical to one found on the RZ/G3S SoC with the
> > difference like it support more External IRQs, GPT Error Interrupts
> > and also has additional registers for GPT/MTU IRQ selection, shared
> > IRQ selection between external IRQ and TINT. Hence new generic
> > compatible string "renesas,r9a08g046-irqc" is added for RZ/G3L SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> > * Simplified the binding using pattern
> > ---
> > .../renesas,rzg2l-irqc.yaml | 42 +++++++++++++++----
> > 1 file changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml index a0b57d808639..311741122b05 100644
> > ---
> > a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l
> > -irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r
> > +++ zg2l-irqc.yaml
> > @@ -30,7 +30,10 @@ properties:
> > - renesas,r9a08g045-irqc # RZ/G3S
> > - const: renesas,rzg2l-irqc
> >
> > - - const: renesas,r9a07g043f-irqc # RZ/Five
> > + - items:
>
> Drop items. The point was to simplify, so just enum.
Agreed.
>
> > + - enum:
> > + - renesas,r9a07g043f-irqc # RZ/Five
> > + - renesas,r9a08g046-irqc # RZ/G3L
> >
> > '#interrupt-cells':
> > description: The first cell should contain a macro
> > RZG2L_{NMI,IRQX} included in the @@ -48,17 +51,17 @@ properties:
> >
> > interrupts:
> > minItems: 45
> > - maxItems: 48
> > + maxItems: 61
> >
> > interrupt-names:
> > minItems: 45
> > - maxItems: 48
> > + maxItems: 61
> > items:
> > oneOf:
> > - description: NMI interrupt
> > const: nmi
> > - description: External IRQ interrupt
> > - pattern: '^irq([0-7])$'
> > + pattern: '^irq([0-9]|1[0-5])$'
> > - description: GPIO interrupt
> > pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
> > - description: Bus error interrupt @@ -75,6 +78,8 @@
> > properties:
> > const: ec7tie2-1
> > - description: ECCRAM1 error overflow interrupt
> > const: ec7tiovf-1
> > + - description: Integrated GPT Error interrupt
> > + pattern: '^ovfunf([0-7])$'
> >
> > clocks:
> > maxItems: 2
> > @@ -106,6 +111,22 @@ required:
> > allOf:
> > - $ref: /schemas/interrupt-controller.yaml#
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r9a07g043f-irqc
> > + - renesas,r9a07g043u-irqc
> > + - renesas,r9a07g044-irqc
> > + - renesas,r9a07g054-irqc
> > + then:
> > + properties:
> > + interrupts:
>
> Missing minitems. Previously it was not 45, was it?
Will add maxItems: 48 as well.
>
> > + maxItems: 48
> > + interrupt-names:
> > + maxItems: 48
> > +
> > - if:
> > properties:
> > compatible:
> > @@ -118,12 +139,19 @@ allOf:
> > maxItems: 45
> > interrupt-names:
> > maxItems: 45
> > - else:
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r9a08g046-irqc
> > + then:
> > properties:
> > interrupts:
> > - minItems: 48
> > + maxItems: 61
>
> minItems instead. Just like it was in the old code.
Agreed. Will send V3 with these changes.
Cheers,
Biju
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names
2026-02-04 18:06 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Biju
@ 2026-02-10 1:14 ` Rob Herring (Arm)
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring (Arm) @ 2026-02-10 1:14 UTC (permalink / raw)
To: Biju
Cc: linux-kernel, linux-renesas-soc, Lad Prabhakar, Magnus Damm,
Biju Das, devicetree, Thomas Gleixner, Conor Dooley,
Krzysztof Kozlowski, Geert Uytterhoeven
On Wed, 04 Feb 2026 18:06:17 +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Simplify the bindings by using pattern property for interrupt-names.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * New patch.
> ---
> .../renesas,rzg2l-irqc.yaml | 120 ++++--------------
> 1 file changed, 23 insertions(+), 97 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-02-10 1:14 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-04 18:06 [PATCH v2 0/9] Add RZ/G3L IRQC support Biju
2026-02-04 18:06 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Biju
2026-02-10 1:14 ` Rob Herring (Arm)
2026-02-04 18:06 ` [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Biju
2026-02-05 13:39 ` Krzysztof Kozlowski
2026-02-06 9:00 ` Biju Das
2026-02-04 18:06 ` [PATCH v2 9/9] arm64: dts: renesas: r9a08g046: Add ICU node Biju
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