From: Yixun Lan <dlan@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Inochi Amaoto <inochiama@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org, Yixun Lan <dlan@kernel.org>
Subject: [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe
Date: Thu, 30 Apr 2026 10:30:25 +0000 [thread overview]
Message-ID: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> (raw)
Here are some fixes for previous patch set in order to make PCIe work,
Add PCIe DBI clock which was missing, Fix the parent clock, And correct
the PCIe Clock CTRL register offset.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (4):
dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
clk: spacemit: k3: Add PCIe DBI clock
clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
clk: spacemit: k3: Fix PCIe clock register offset
drivers/clk/spacemit/ccu-k3.c | 30 +++++++++++++++++---------
include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++
include/soc/spacemit/k3-syscon.h | 4 ++--
3 files changed, 27 insertions(+), 12 deletions(-)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260430-06-pci-clk-fix-e60487b07607
Best regards,
--
Yixun Lan <dlan@kernel.org>
next reply other threads:[~2026-04-30 10:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 10:30 Yixun Lan [this message]
2026-04-30 10:30 ` [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
2026-04-30 18:55 ` Conor Dooley
2026-05-02 11:32 ` Yixun Lan
2026-05-03 17:59 ` Conor Dooley
2026-04-30 10:30 ` [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Yixun Lan
2026-05-01 9:28 ` Krzysztof Kozlowski
2026-05-02 11:30 ` Yixun Lan
2026-04-30 10:30 ` [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Yixun Lan
2026-04-30 10:30 ` [PATCH 4/4] clk: spacemit: k3: Fix PCIe clock register offset Yixun Lan
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