From: Yixun Lan <dlan@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Inochi Amaoto <inochiama@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org, Yixun Lan <dlan@kernel.org>
Subject: [PATCH 4/4] clk: spacemit: k3: Fix PCIe clock register offset
Date: Thu, 30 Apr 2026 10:30:29 +0000 [thread overview]
Message-ID: <20260430-06-pci-clk-fix-v1-4-32fdc77c02ab@kernel.org> (raw)
In-Reply-To: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org>
The offset of PCIe Clock CTRL register for port B and C controller was
wrongle swapped, correct it here.
Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
include/soc/spacemit/k3-syscon.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h
index 0299bea065a0..a68255dd641f 100644
--- a/include/soc/spacemit/k3-syscon.h
+++ b/include/soc/spacemit/k3-syscon.h
@@ -168,8 +168,8 @@
#define APMU_CPU_C2_CLK_CTRL 0x394
#define APMU_CPU_C3_CLK_CTRL 0x208
#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0
-#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8
-#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0
+#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0
+#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0
#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
--
2.53.0
prev parent reply other threads:[~2026-04-30 10:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 10:30 [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
2026-04-30 10:30 ` [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
2026-04-30 18:55 ` Conor Dooley
2026-05-02 11:32 ` Yixun Lan
2026-05-03 17:59 ` Conor Dooley
2026-04-30 10:30 ` [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Yixun Lan
2026-05-01 9:28 ` Krzysztof Kozlowski
2026-05-02 11:30 ` Yixun Lan
2026-04-30 10:30 ` [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Yixun Lan
2026-04-30 10:30 ` Yixun Lan [this message]
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