* [PATCH v5 1/5] dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible
2026-04-29 7:43 [PATCH v5 0/5] media: iris: add support for purwa platform Wangao Wang
@ 2026-04-29 7:43 ` Wangao Wang
2026-04-30 7:38 ` Krzysztof Kozlowski
2026-04-29 7:43 ` [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100 Wangao Wang
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Wangao Wang @ 2026-04-29 7:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang,
Bryan O'Donoghue
Document the new compatible string "qcom,x1p42100-iris".
Unlike SM8550 where the BSE (Bitstream Engine) is clocked implicitly
via vcodec0_core, x1p42100 exposes a dedicated BSE clock vcodec0_bse
that requires explicit enable/disable and frequency configuration.
The SM8550 driver has no knowledge of this clock and therefore cannot
operate x1p42100 hardware correctly.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
.../bindings/media/qcom,sm8550-iris.yaml | 23 +++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
index 9c4b760508b50251ac467ad44a366689260bfc0d..0400ca1bff05dcef6b742c3fbf77e38adca9f280 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,qcs8300-iris
- qcom,sm8550-iris
- qcom,sm8650-iris
+ - qcom,x1p42100-iris
reg:
maxItems: 1
@@ -41,13 +42,16 @@ properties:
- const: mmcx
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
clock-names:
+ minItems: 3
items:
- const: iface
- const: core
- const: vcodec0_core
+ - const: vcodec0_bse
firmware-name:
maxItems: 1
@@ -115,6 +119,23 @@ allOf:
maxItems: 1
reset-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,x1p42100-iris
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+ else:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 1/5] dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible
2026-04-29 7:43 ` [PATCH v5 1/5] dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible Wangao Wang
@ 2026-04-30 7:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2026-04-30 7:38 UTC (permalink / raw)
To: Wangao Wang
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
linux-media, linux-arm-msm, devicetree, linux-kernel,
Bryan O'Donoghue
On Wed, Apr 29, 2026 at 03:43:52PM +0800, Wangao Wang wrote:
> Document the new compatible string "qcom,x1p42100-iris".
>
> Unlike SM8550 where the BSE (Bitstream Engine) is clocked implicitly
> via vcodec0_core, x1p42100 exposes a dedicated BSE clock vcodec0_bse
> that requires explicit enable/disable and frequency configuration.
> The SM8550 driver has no knowledge of this clock and therefore cannot
> operate x1p42100 hardware correctly.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,sm8550-iris.yaml | 23 +++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100
2026-04-29 7:43 [PATCH v5 0/5] media: iris: add support for purwa platform Wangao Wang
2026-04-29 7:43 ` [PATCH v5 1/5] dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible Wangao Wang
@ 2026-04-29 7:43 ` Wangao Wang
2026-04-30 8:09 ` Dikshita Agarwal
2026-04-29 7:43 ` [PATCH v5 3/5] media: iris: Add platform data " Wangao Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Wangao Wang @ 2026-04-29 7:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang,
Bryan O'Donoghue
On X1P42100 the Iris block has an extra BSE clock. Wire this clock into
the power on/off sequence.
The BSE clock is used to drive the Bin Stream Engine, which is a sub-block
of the video codec hardware responsible for bitstream-level processing. It
is required to be enabled separately from the core clock to ensure proper
codec operation.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_common.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 548e5f1727fdb7543f76a1871f17257fa2360733..281b1f54cb962dedbfb0ec96ed3a5aab99b50eb8 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -224,6 +224,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
{
dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_HW_CLK);
}
@@ -292,12 +293,18 @@ int iris_vpu_power_on_hw(struct iris_core *core)
if (ret && ret != -ENOENT)
goto err_disable_hw_clock;
+ ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK);
+ if (ret && ret != -ENOENT)
+ goto err_disable_hw_ahb_clock;
+
ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
if (ret)
- goto err_disable_hw_ahb_clock;
+ goto err_disable_bse_hw_clock;
return 0;
+err_disable_bse_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
err_disable_hw_ahb_clock:
iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
err_disable_hw_clock:
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100
2026-04-29 7:43 ` [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100 Wangao Wang
@ 2026-04-30 8:09 ` Dikshita Agarwal
0 siblings, 0 replies; 9+ messages in thread
From: Dikshita Agarwal @ 2026-04-30 8:09 UTC (permalink / raw)
To: Wangao Wang, Bryan O'Donoghue, Vikash Garodia, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Bryan O'Donoghue
On 4/29/2026 1:13 PM, Wangao Wang wrote:
> On X1P42100 the Iris block has an extra BSE clock. Wire this clock into
> the power on/off sequence.
>
> The BSE clock is used to drive the Bin Stream Engine, which is a sub-block
> of the video codec hardware responsible for bitstream-level processing. It
> is required to be enabled separately from the core clock to ensure proper
> codec operation.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index 548e5f1727fdb7543f76a1871f17257fa2360733..281b1f54cb962dedbfb0ec96ed3a5aab99b50eb8 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -224,6 +224,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
> {
> dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
> iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
> iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> }
> @@ -292,12 +293,18 @@ int iris_vpu_power_on_hw(struct iris_core *core)
> if (ret && ret != -ENOENT)
> goto err_disable_hw_clock;
>
> + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK);
> + if (ret && ret != -ENOENT)
> + goto err_disable_hw_ahb_clock;
> +
> ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
> if (ret)
> - goto err_disable_hw_ahb_clock;
> + goto err_disable_bse_hw_clock;
>
> return 0;
>
> +err_disable_bse_hw_clock:
> + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
> err_disable_hw_ahb_clock:
> iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> err_disable_hw_clock:
>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Thanks,
Dikshita
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 3/5] media: iris: Add platform data for X1P42100
2026-04-29 7:43 [PATCH v5 0/5] media: iris: add support for purwa platform Wangao Wang
2026-04-29 7:43 ` [PATCH v5 1/5] dt-bindings: media: qcom,sm8550-iris: Add X1P42100 compatible Wangao Wang
2026-04-29 7:43 ` [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100 Wangao Wang
@ 2026-04-29 7:43 ` Wangao Wang
2026-04-30 10:53 ` Dikshita Agarwal
2026-04-29 7:43 ` [PATCH v5 4/5] arm64: dts: qcom: purwa: Override Iris clocks and operating points Wangao Wang
2026-04-29 7:43 ` [PATCH v5 5/5] arm64: dts: qcom: purwa-iot-som: enable video Wangao Wang
4 siblings, 1 reply; 9+ messages in thread
From: Wangao Wang @ 2026-04-29 7:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Introduce platform data for X1P42100, derived from SM8550 but using a
different clock configuration and a dedicated OPP setup.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_gen2.c | 97 ++++++++++++++++++++++
.../platform/qcom/iris/iris_platform_x1p42100.h | 22 +++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
4 files changed, 124 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5a489917580eb10022fdcb52f7321a915e8b239d..2e97360ddcd56a4b61fb296782b0c914b6154784 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -47,6 +47,7 @@ extern const struct iris_platform_data sm8250_data;
extern const struct iris_platform_data sm8550_data;
extern const struct iris_platform_data sm8650_data;
extern const struct iris_platform_data sm8750_data;
+extern const struct iris_platform_data x1p42100_data;
enum platform_clk_type {
IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 5da90d47f9c6eab4a7e6b17841fdc0e599397bf7..e8b1b92a6329266d22b06e84c47c477d1a9d742e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -15,6 +15,7 @@
#include "iris_platform_qcs8300.h"
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
+#include "iris_platform_x1p42100.h"
#define VIDEO_ARCH_LX 1
#define BITRATE_MAX 245000000
@@ -1317,3 +1318,99 @@ const struct iris_platform_data qcs8300_data = {
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
+
+const struct iris_platform_data x1p42100_data = {
+ .get_instance = iris_hfi_gen2_get_instance,
+ .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
+ .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu3_ops,
+ .set_preset_registers = iris_set_sm8550_preset_registers,
+ .icc_tbl = sm8550_icc_table,
+ .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
+ .clk_rst_tbl = sm8550_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
+ .bw_tbl_dec = sm8550_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
+ .pmdomain_tbl = sm8550_pmdomain_table,
+ .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+ .opp_pd_tbl = sm8550_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
+ .clk_tbl = x1p42100_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table),
+ .opp_clk_tbl = x1p42100_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu30_p4.mbn",
+ .pas_id = IRIS_PAS_ID,
+ .inst_iris_fmts = platform_fmts_sm8550_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
+ .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
+ .core_arch = VIDEO_ARCH_LX,
+ .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+ .ubwc_config = &ubwc_config_sm8550,
+ .num_vpp_pipe = 1,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+ .dec_input_config_params_default =
+ sm8550_vdec_input_config_params_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+ .dec_input_config_params_hevc =
+ sm8550_vdec_input_config_param_hevc,
+ .dec_input_config_params_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+ .dec_input_config_params_vp9 =
+ sm8550_vdec_input_config_param_vp9,
+ .dec_input_config_params_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
+ .dec_output_config_params =
+ sm8550_vdec_output_config_params,
+ .dec_output_config_params_size =
+ ARRAY_SIZE(sm8550_vdec_output_config_params),
+
+ .enc_input_config_params =
+ sm8550_venc_input_config_params,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8550_venc_input_config_params),
+ .enc_output_config_params =
+ sm8550_venc_output_config_params,
+ .enc_output_config_params_size =
+ ARRAY_SIZE(sm8550_venc_output_config_params),
+
+ .dec_input_prop = sm8550_vdec_subscribe_input_properties,
+ .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+ .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+ .dec_output_prop_avc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+ .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+ .dec_output_prop_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+ .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+ .dec_output_prop_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
+
+ .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+
+ .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
+ .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
+ .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+ .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h
new file mode 100644
index 0000000000000000000000000000000000000000..d89acfbc1233dad0692f6c13c3fc22b10e5bdd80
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __IRIS_PLATFORM_X1P42100_H__
+#define __IRIS_PLATFORM_X1P42100_H__
+
+static const struct platform_clk_data x1p42100_clk_table[] = {
+ {IRIS_AXI_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_BSE_HW_CLK, "vcodec0_bse" },
+};
+
+static const char *const x1p42100_opp_clk_table[] = {
+ "vcodec0_core",
+ "vcodec0_bse",
+ NULL,
+};
+
+#endif
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ddaacda523ecb9990af0dd0640196223fbcc2cab..287f615dfa6479964ed68649f2829b5bbeed6cd6 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -374,6 +374,10 @@ static const struct of_device_id iris_dt_match[] = {
.compatible = "qcom,sm8750-iris",
.data = &sm8750_data,
},
+ {
+ .compatible = "qcom,x1p42100-iris",
+ .data = &x1p42100_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, iris_dt_match);
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 3/5] media: iris: Add platform data for X1P42100
2026-04-29 7:43 ` [PATCH v5 3/5] media: iris: Add platform data " Wangao Wang
@ 2026-04-30 10:53 ` Dikshita Agarwal
0 siblings, 0 replies; 9+ messages in thread
From: Dikshita Agarwal @ 2026-04-30 10:53 UTC (permalink / raw)
To: Wangao Wang, Bryan O'Donoghue, Vikash Garodia, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
On 4/29/2026 1:13 PM, Wangao Wang wrote:
> Introduce platform data for X1P42100, derived from SM8550 but using a
> different clock configuration and a dedicated OPP setup.
>
> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 97 ++++++++++++++++++++++
> .../platform/qcom/iris/iris_platform_x1p42100.h | 22 +++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 4 files changed, 124 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 5a489917580eb10022fdcb52f7321a915e8b239d..2e97360ddcd56a4b61fb296782b0c914b6154784 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -47,6 +47,7 @@ extern const struct iris_platform_data sm8250_data;
> extern const struct iris_platform_data sm8550_data;
> extern const struct iris_platform_data sm8650_data;
> extern const struct iris_platform_data sm8750_data;
> +extern const struct iris_platform_data x1p42100_data;
>
> enum platform_clk_type {
> IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 5da90d47f9c6eab4a7e6b17841fdc0e599397bf7..e8b1b92a6329266d22b06e84c47c477d1a9d742e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -15,6 +15,7 @@
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
> +#include "iris_platform_x1p42100.h"
>
> #define VIDEO_ARCH_LX 1
> #define BITRATE_MAX 245000000
> @@ -1317,3 +1318,99 @@ const struct iris_platform_data qcs8300_data = {
> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
Add a comment to mention what is different from sm8550 data.
> +
> +const struct iris_platform_data x1p42100_data = {
> + .get_instance = iris_hfi_gen2_get_instance,
> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu3_ops,
> + .set_preset_registers = iris_set_sm8550_preset_registers,
> + .icc_tbl = sm8550_icc_table,
> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> + .clk_rst_tbl = sm8550_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
> + .bw_tbl_dec = sm8550_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> + .pmdomain_tbl = sm8550_pmdomain_table,
> + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> + .opp_pd_tbl = sm8550_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> + .clk_tbl = x1p42100_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table),
> + .opp_clk_tbl = x1p42100_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu30_p4.mbn",
is this the correct firmware? shouldn't it be vpu30_p1.mbn?
Thanks,
Dikshita
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 4/5] arm64: dts: qcom: purwa: Override Iris clocks and operating points
2026-04-29 7:43 [PATCH v5 0/5] media: iris: add support for purwa platform Wangao Wang
` (2 preceding siblings ...)
2026-04-29 7:43 ` [PATCH v5 3/5] media: iris: Add platform data " Wangao Wang
@ 2026-04-29 7:43 ` Wangao Wang
2026-04-29 7:43 ` [PATCH v5 5/5] arm64: dts: qcom: purwa-iot-som: enable video Wangao Wang
4 siblings, 0 replies; 9+ messages in thread
From: Wangao Wang @ 2026-04-29 7:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang,
Konrad Dybcio, Dmitry Baryshkov
The Iris block on X1P differs from SM8550/X1E in its clock configuration
and requires a dedicated OPP table. The node inherited from the X1E cannot
be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot
be applied.
Override the inherited clocks, clock-names, and operating points, and
replaces them with the X1P42100-specific definitions. A new OPP table
is provided to support the correct performance levels on this platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/purwa.dtsi | 50 +++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi
index ea65b8448836ead83f837e973ed536e8ea0ed8ef..a503deec97d75dcfb6792b007e0b74e517404cfc 100644
--- a/arch/arm64/boot/dts/qcom/purwa.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa.dtsi
@@ -21,6 +21,7 @@
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
+/delete-node/ &iris_opp_table;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_aoss3;
/delete-node/ &thermal_cpu2_0_btm;
@@ -167,6 +168,55 @@ &gpucc {
compatible = "qcom,x1p42100-gpucc";
};
+&iris {
+ compatible = "qcom,x1p42100-iris";
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&videocc VIDEO_CC_MVS0_BSE_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "vcodec0_bse";
+
+ operating-points-v2 = <&iris_opp_table_x1p42100>;
+
+ iris_opp_table_x1p42100: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-210000000 {
+ opp-hz = /bits/ 64 <210000000 105000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000 150000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-335000000 {
+ opp-hz = /bits/ 64 <335000000 167500000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-424000000 {
+ opp-hz = /bits/ 64 <424000000 212000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000 250000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_turbo>;
+ };
+ };
+};
+
/* PCIe3 has half the lanes compared to X1E80100 */
&pcie3 {
num-lanes = <4>;
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v5 5/5] arm64: dts: qcom: purwa-iot-som: enable video
2026-04-29 7:43 [PATCH v5 0/5] media: iris: add support for purwa platform Wangao Wang
` (3 preceding siblings ...)
2026-04-29 7:43 ` [PATCH v5 4/5] arm64: dts: qcom: purwa: Override Iris clocks and operating points Wangao Wang
@ 2026-04-29 7:43 ` Wangao Wang
4 siblings, 0 replies; 9+ messages in thread
From: Wangao Wang @ 2026-04-29 7:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang,
Dmitry Baryshkov, Konrad Dybcio, Krzysztof Kozlowski
Enable video nodes on the purwa-iot-som board.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
index 394e65518ac5037e5c7c50583acefc0dbc8ebb47..ff8621f8750584636ad781467f9c35ace2354e4c 100644
--- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
@@ -389,6 +389,10 @@ &gpu_zap_shader {
firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
};
+&iris {
+ status = "okay";
+};
+
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread