* [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC
@ 2026-05-06 8:59 Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Changhuang Liang @ 2026-05-06 8:59 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
StarFive JHB100 SoC consists of 4 RISC-V low power Cores (Dubhe-70). It
also features various interfaces such as I2C, SPI, CAN, USB, MMC, Uart,
etc.
This patch series introduces initial SoC DTSI support for the StarFive
JHB100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI.
- StarFive Dubhe-70 CPU
- PMU
- PLIC
- CLINT
- UART
- INTC
changes since v1:
patch 2
- Remove from the current series, as it has already been applied.
patch 3:
- Add Conor's Acked-by tag.
patch 5:
- Change jhb100-evb1.dtsi to jhb100-evb1.dts.
- Change "Maintained" to "Supported".
- Add intc node to handle the interrupt of UART.
- Update fixed-clock node name.
- Move reg after compatible.
v1: https://lore.kernel.org/all/20260402084019.440708-1-changhuang.liang@starfivetech.com/
Ji Sheng Teoh (1):
dt-bindings: riscv: Add StarFive Dubhe-70 compatibles
Ley Foon Tan (3):
dt-bindings: interrupt-controller: Add StarFive JHB100 plic
dt-bindings: riscv: Add StarFive JHB100 SoC
riscv: dts: starfive: jhb100: Add JHB100 base DT
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/starfive.yaml | 5 +
MAINTAINERS | 6 +
arch/riscv/boot/dts/starfive/Makefile | 2 +
arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 32 ++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 337 ++++++++++++++++++
7 files changed, 384 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
base-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
@ 2026-05-06 8:59 ` Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 2/4] dt-bindings: interrupt-controller: Add StarFive JHB100 plic Changhuang Liang
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Changhuang Liang @ 2026-05-06 8:59 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
From: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Add new compatible string for Dubhe-70.
Dubhe-70 is a low power RISC-V cpu core from StarFive Technology.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..e7eda7a9c345 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,7 @@ properties:
- sifive,u74-mc
- spacemit,x100
- spacemit,x60
+ - starfive,dubhe-70
- thead,c906
- thead,c908
- thead,c910
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] dt-bindings: interrupt-controller: Add StarFive JHB100 plic
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
@ 2026-05-06 8:59 ` Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 3/4] dt-bindings: riscv: Add StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
3 siblings, 0 replies; 6+ messages in thread
From: Changhuang Liang @ 2026-05-06 8:59 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add compatible string for StarFive JHB100 plic.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 639bbeb1f6bd..4a242d252aef 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
- spacemit,k1-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
+ - starfive,jhb100-plic
- tenstorrent,blackhole-plic
- const: sifive,plic-1.0.0
- items:
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] dt-bindings: riscv: Add StarFive JHB100 SoC
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 2/4] dt-bindings: interrupt-controller: Add StarFive JHB100 plic Changhuang Liang
@ 2026-05-06 8:59 ` Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
3 siblings, 0 replies; 6+ messages in thread
From: Changhuang Liang @ 2026-05-06 8:59 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add device tree bindings for the StarFive JHB100 RISC-V SoC.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 8ba0e10b529a..277618efff6e 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -43,6 +43,11 @@ properties:
- const: starfive,jh7110s
- const: starfive,jh7110
+ - items:
+ - enum:
+ - starfive,jhb100-evb1
+ - const: starfive,jhb100
+
additionalProperties: true
...
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
` (2 preceding siblings ...)
2026-05-06 8:59 ` [PATCH v2 3/4] dt-bindings: riscv: Add StarFive JHB100 SoC Changhuang Liang
@ 2026-05-06 8:59 ` Changhuang Liang
2026-05-06 17:44 ` Conor Dooley
3 siblings, 1 reply; 6+ messages in thread
From: Changhuang Liang @ 2026-05-06 8:59 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
PMU, UART, INTC and 1GB DDR.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 +
arch/riscv/boot/dts/starfive/Makefile | 2 +
arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 32 ++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 337 +++++++++++++++++++
4 files changed, 377 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 0dfad67f66c0..22e34d2ad696 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25588,6 +25588,12 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
+STARFIVE JHB100 DEVICETREES
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+L: linux-riscv@lists.infradead.org
+S: Supported
+F: arch/riscv/boot/dts/starfive/jhb100*
+
STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Supported
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 3dd1f05283f7..42841942fe54 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1.dtb
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
new file mode 100644
index 000000000000..462b6fb7953b
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100.dtsi"
+
+/ {
+ model = "StarFive JHB100 EVB-1";
+ compatible = "starfive,jhb100-evb1", "starfive,jhb100";
+
+ aliases {
+ serial6 = &uart6;
+ };
+
+ chosen {
+ stdout-path = "serial6:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <5000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x40000000>; /* 1GB */
+ };
+};
+
+&uart6 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
new file mode 100644
index 000000000000..4133ba1f45b4
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "starfive,jhb100";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "starfive,dubhe-70", "riscv";
+ reg = <0x0>;
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c0>;
+ tlb-split;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "starfive,dubhe-70", "riscv";
+ reg = <0x1>;
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c1>;
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "starfive,dubhe-70", "riscv";
+ reg = <0x2>;
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c2>;
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "starfive,dubhe-70", "riscv";
+ reg = <0x3>;
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintpause",
+ "zihpm", "svinval", "svnapot", "sscofpmf";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <16>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <24>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&l2c3>;
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ l2c0: cache-controller-0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c1: cache-controller-1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c2: cache-controller-2 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2c3: cache-controller-3 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x20000>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: cache-controller-4 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <1024>;
+ cache-size = <0x20000>;
+ cache-unified;
+ };
+ };
+
+ pmu {
+ compatible = "riscv,pmu";
+ interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>,
+ <&cpu2_intc 13>, <&cpu3_intc 13>;
+
+ riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+ <0x00006 0x0000 0xB>,
+ <0x00008 0x0000 0x10>,
+ <0x00009 0x0000 0xF>,
+ <0x10000 0x0000 0x19>,
+ <0x10001 0x0000 0x1A>,
+ <0x10002 0x0000 0x1B>,
+ <0x10003 0x0000 0x1C>,
+ <0x10008 0x0000 0x8>,
+ <0x10009 0x0000 0x9>,
+ <0x1000C 0x0000 0x9E>,
+ <0x1000D 0x0000 0x9F>,
+ <0x10010 0x0000 0x1D>,
+ <0x10011 0x0000 0x1E>,
+ <0x10012 0x0000 0x1F>,
+ <0x10013 0x0000 0x20>,
+ <0x10014 0x0000 0x21>,
+ <0x10018 0x0000 0x17>,
+ <0x10019 0x0000 0x18>,
+ <0x10020 0x0000 0x8>,
+ <0x10021 0x0000 0x7>;
+
+ riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+ <0x00008 0x00009 0x00007FF8>,
+ <0x10000 0x10003 0x00007FF8>,
+ <0x10008 0x10009 0x00007FF8>,
+ <0x1000C 0x1000D 0x00007FF8>,
+ <0x10010 0x10014 0x00007FF8>,
+ <0x10018 0x10019 0x00007FF8>,
+ <0x10020 0x10021 0x00007FF8>;
+
+ riscv,raw-event-to-mhpmcounters =
+ <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */
+ <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */
+ <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
+ };
+
+ clk_uart: clock-25000000 {
+ compatible = "fixed-clock"; /* Initial clock handler for UART */
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ clint: timer@2000000 {
+ compatible = "starfive,jhb100-clint", "sifive,clint0";
+ reg = <0x0 0x02000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x0c000000 0x0 0x4000000>;
+ riscv,ndev = <400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ };
+
+ bus_nioc: bus_nioc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
+ <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
+ ranges;
+
+ uart6: serial@11982000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x11982000 0x0 0x400>;
+ clocks = <&clk_uart>, <&clk_uart>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <26>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@13220000 {
+ compatible = "starfive,jhb100-intc";
+ reg = <0x0 0x13220000 0x0 0x80>;
+ interrupts = <1>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT
2026-05-06 8:59 ` [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
@ 2026-05-06 17:44 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2026-05-06 17:44 UTC (permalink / raw)
To: Changhuang Liang
Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing, Yixun Lan,
Joel Stanley, Drew Fustini, Darshan Prajapati, Guodong Xu,
Michal Simek, Junhui Liu, Heinrich Schuchardt, E Shattow,
Icenowy Zheng, Anup Patel, linux-kernel, devicetree, linux-riscv,
Ji Sheng Teoh, Hal Feng, Ley Foon Tan, Michael Zhu
[-- Attachment #1: Type: text/plain, Size: 8823 bytes --]
On Wed, May 06, 2026 at 01:59:37AM -0700, Changhuang Liang wrote:
> From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
>
> Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
> PMU, UART, INTC and 1GB DDR.
>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> MAINTAINERS | 6 +
> arch/riscv/boot/dts/starfive/Makefile | 2 +
> arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 32 ++
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 337 +++++++++++++++++++
> 4 files changed, 377 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0dfad67f66c0..22e34d2ad696 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25588,6 +25588,12 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> F: drivers/phy/starfive/phy-jh7110-pcie.c
> F: drivers/phy/starfive/phy-jh7110-usb.c
>
> +STARFIVE JHB100 DEVICETREES
> +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> +L: linux-riscv@lists.infradead.org
> +S: Supported
> +F: arch/riscv/boot/dts/starfive/jhb100*
> +
> STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
> M: Changhuang Liang <changhuang.liang@starfivetech.com>
> S: Supported
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 3dd1f05283f7..42841942fe54 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> +
> +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> new file mode 100644
> index 000000000000..462b6fb7953b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100.dtsi"
> +
> +/ {
> + model = "StarFive JHB100 EVB-1";
> + compatible = "starfive,jhb100-evb1", "starfive,jhb100";
> +
> + aliases {
> + serial6 = &uart6;
> + };
> +
> + chosen {
> + stdout-path = "serial6:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <5000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x0 0x40000000>; /* 1GB */
> + };
> +};
> +
> +&uart6 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> new file mode 100644
> index 000000000000..4133ba1f45b4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -0,0 +1,337 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + compatible = "starfive,jhb100";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "starfive,dubhe-70", "riscv";
> + reg = <0x0>;
> + riscv,isa = "rv64imafdcbh";
Please just remove this property.
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
> + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintpause",
> + "zihpm", "svinval", "svnapot", "sscofpmf";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <16>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <512>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <24>;
> + mmu-type = "riscv,sv48";
> + next-level-cache = <&l2c0>;
> + tlb-split;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + };
Each cpu is in a different cluster? Interesting, suppose it makes sense
when you have different l2 caches. What other resources are not shared?
Do they have different cpu clocks too etc?
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu1>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpu2>;
> + };
> + };
> +
> + cluster3 {
> + core0 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + l2c0: cache-controller-0 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c1: cache-controller-1 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c2: cache-controller-2 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c3: cache-controller-3 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l3_cache: cache-controller-4 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <3>;
> + cache-sets = <1024>;
> + cache-size = <0x20000>;
> + cache-unified;
> + };
> + };
> + clk_uart: clock-25000000 {
> + compatible = "fixed-clock"; /* Initial clock handler for UART */
What does this comment mean?
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges;
> + ranges;
> +
> + clint: timer@2000000 {
> + compatible = "starfive,jhb100-clint", "sifive,clint0";
> + reg = <0x0 0x02000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>;
> + };
> +
> + plic: interrupt-controller@c000000 {
> + compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0x0c000000 0x0 0x4000000>;
> + riscv,ndev = <400>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>;
> + };
> +
> + bus_nioc: bus_nioc {
jhb100-evb1.dtb: bus_nioc (simple-bus): $nodename:0: 'bus_nioc' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$'
from schema $id: http://devicetree.org/schemas/simple-bus.yaml
Cheers,
Conor.
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
> + <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
> + ranges;
> +
> + uart6: serial@11982000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x11982000 0x0 0x400>;
> + clocks = <&clk_uart>, <&clk_uart>;
> + clock-names = "baudclk", "apb_pclk";
> + interrupt-parent = <&intc>;
> + interrupts = <26>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@13220000 {
> + compatible = "starfive,jhb100-intc";
> + reg = <0x0 0x13220000 0x0 0x80>;
> + interrupts = <1>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +};
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-05-06 17:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 2/4] dt-bindings: interrupt-controller: Add StarFive JHB100 plic Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 3/4] dt-bindings: riscv: Add StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
2026-05-06 17:44 ` Conor Dooley
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