[PATCH] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[PATCH] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[Pramod Maurya]

Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080).
The binding documents the three supported compatible strings and all
vendor-specific properties that the axis-fifo driver reads from the
device tree.

This resolves the following checkpatch.pl warnings in
drivers/staging/axis-fifo/axis-fifo.c:
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documented

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 92 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
new file mode 100644
index 000000000000..1e07db9cd456
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI-Stream FIFO
+
+maintainers:
+  - Jacob Feder <jacobsfeder@gmail.com>
+
+description:
+  The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to
+  an AXI-Stream FIFO IP core. It allows a processor to transmit and receive
+  AXI-Stream packets via simple MMIO register reads and writes.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,axi-fifo-mm-s-4.1
+      - xlnx,axi-fifo-mm-s-4.2
+      - xlnx,axi-fifo-mm-s-4.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  xlnx,axi-str-rxd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Width of the receive AXI-Stream data bus in bits. Currently only 32
+      is supported.
+    const: 32
+
+  xlnx,axi-str-txd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Width of the transmit AXI-Stream data bus in bits. Currently only 32
+      is supported.
+    const: 32
+
+  xlnx,rx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of the receive FIFO in words.
+
+  xlnx,tx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of the transmit FIFO in words.
+
+  xlnx,use-rx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Set to 1 if the receive data FIFO is enabled, 0 otherwise.
+    enum: [0, 1]
+
+  xlnx,use-tx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Set to 1 if the transmit data FIFO is enabled, 0 otherwise.
+    enum: [0, 1]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - xlnx,axi-str-rxd-tdata-width
+  - xlnx,axi-str-txd-tdata-width
+  - xlnx,rx-fifo-depth
+  - xlnx,tx-fifo-depth
+  - xlnx,use-rx-data
+  - xlnx,use-tx-data
+
+additionalProperties: false
+
+examples:
+  - |
+    axi_fifo: fifo@43c00000 {
+        compatible = "xlnx,axi-fifo-mm-s-4.3";
+        reg = <0x43c00000 0x10000>;
+        interrupts = <0 30 4>;
+        interrupt-parent = <&gic>;
+        xlnx,axi-str-rxd-tdata-width = <32>;
+        xlnx,axi-str-txd-tdata-width = <32>;
+        xlnx,rx-fifo-depth = <0x1000>;
+        xlnx,tx-fifo-depth = <0x1000>;
+        xlnx,use-rx-data = <1>;
+        xlnx,use-tx-data = <1>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9b107057ad8c..84be7c8ae257 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29130,6 +29130,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
 F:	drivers/net/ethernet/xilinx/xilinx_axienet*
 
+XILINX AXI-STREAM FIFO DRIVER
+M:	Jacob Feder <jacobsfeder@gmail.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
+F:	drivers/staging/axis-fifo/
+
 XILINX CAN DRIVER
 M:	Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
 L:	linux-can@vger.kernel.org
-- 
2.52.0

Re: [PATCH] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] DT Binding ABI Breakage and Duplicate Documentation
- [High] IRQ Race Condition Dropping Unhandled Interrupts
- [High] Incorrect MMIO Accessor Semantics for FIFOs
- [High] Missing Clock Definition and Enablement
--

commit 31b86c7f3095299d0d2eedef1065b0b06442005b
Author: Pramod Maurya <pramod.nexgen@gmail.com>

dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080).
The binding documents the three supported compatible strings and all
vendor-specific properties that the axis-fifo driver reads from the
device tree.

> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 0000000000000..1e07db9cd4565
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI-Stream FIFO
> +
> +maintainers:
> +  - Jacob Feder <jacobsfeder@gmail.com>
> +
> +description:
> +  The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to
> +  an AXI-Stream FIFO IP core. It allows a processor to transmit and receive
> +  AXI-Stream packets via simple MMIO register reads and writes.

Does the driver use the correct MMIO accessors for the FIFO data?

drivers/staging/axis-fifo/axis-fifo.c:axis_fifo_write() {
    ...
	for (int i = 0; i < words_to_write; ++i)
        // driver loops over the stream data offsets using iowrite32
    ...
}

According to the I/O Accessors subsystem guidelines, FIFOs and stream-oriented
hardware must exclusively use stream accessors (e.g., ioread32_rep(), readsl())
to preserve memory-to-device byte order.

Since the driver loops over the stream data offsets using ioread32() and
iowrite32(), won't these accessors enforce CPU-to-device endianness conversion
and cause data payloads to be incorrectly byte-swapped on big-endian
architectures?

[ ... ]

> +properties:
> +  compatible:
> +    enum:
> +      - xlnx,axi-fifo-mm-s-4.1
> +      - xlnx,axi-fifo-mm-s-4.2
> +      - xlnx,axi-fifo-mm-s-4.3
> +
> +  reg:
> +    maxItems: 1

Does the binding need a clocks property to avoid a regression on power
management?

The Xilinx AXI-Stream FIFO is an AXI peripheral that requires an active AXI
clock (e.g., s_axi_aclk) to perform register transactions.

In the driver, axis_fifo_probe() maps the registers and performs MMIO writes
without requesting or enabling a clock via clk_prepare_enable().

If the clock is disabled by the bootloader or a power management unit, won't
these register accesses cause a synchronous external abort and crash or hang
the system?

> +
> +  interrupts:
> +    maxItems: 1

Does the driver's interrupt handler have a regression where unhandled
interrupts are dropped?

drivers/staging/axis-fifo/axis-fifo.c:axis_fifo_irq() {
    ...
	ier = ioread32(fifo->base_addr + XLLF_IER_OFFSET);
	isr = ioread32(fifo->base_addr + XLLF_ISR_OFFSET);
	intr = ier & isr;
    ...
	iowrite32(XLLF_INT_CLEAR_ALL, fifo->base_addr + XLLF_ISR_OFFSET);

	return IRQ_HANDLED;
}

Because XLLF_ISR_OFFSET is a Write-1-to-Clear register, unconditionally writing
0xFFFFFFFF (XLLF_INT_CLEAR_ALL) acknowledges and clears all interrupts, including
any new ones that the hardware asserted between the read and the write.

If a TX or RX complete interrupt fires in this narrow window, won't it be cleared
without being handled, causing the wait_event_interruptible() threads to hang?

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +  - xlnx,use-rx-data
> +  - xlnx,use-tx-data
> +
> +additionalProperties: false

Will this cause a regression for existing device trees?

The original text binding in drivers/staging/axis-fifo/axis-fifo.txt required
properties such as interrupt-names, xlnx,axi-str-rxd-protocol,
xlnx,has-axis-tkeep, and many others describing physical hardware parameters
generated by Xilinx synthesis tools.

By omitting these properties while setting additionalProperties to false, won't
this cause spurious dtbs_check validation errors for existing, correctly formed
device trees?

Additionally, since the legacy axis-fifo.txt file is not deleted in this
commit, does this create duplicate and conflicting sources of truth for the
hardware?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260509171648.46933-1-pramod.nexgen@gmail.com?part=1

Re: [PATCH] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4958 bytes --]

On Sat, May 09, 2026 at 01:16:46PM -0400, Pramod Maurya wrote:
> Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080).
> The binding documents the three supported compatible strings and all
> vendor-specific properties that the axis-fifo driver reads from the
> device tree.
> 
> This resolves the following checkpatch.pl warnings in
> drivers/staging/axis-fifo/axis-fifo.c:
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documented
> 
> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>

Someone else submitted this conversion (which it is, despite you not
removing the old file), and the commentary I provided for that patch
applies here too:
https://lore.kernel.org/all/20260227-unboxed-customary-7ce6eda1858c@spud/

pw-bot: changes-requested

Thanks,
Conor.

> ---
>  .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 92 +++++++++++++++++++
>  MAINTAINERS                                   |  6 ++
>  2 files changed, 98 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> 
> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 000000000000..1e07db9cd456
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI-Stream FIFO
> +
> +maintainers:
> +  - Jacob Feder <jacobsfeder@gmail.com>
> +
> +description:
> +  The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to
> +  an AXI-Stream FIFO IP core. It allows a processor to transmit and receive
> +  AXI-Stream packets via simple MMIO register reads and writes.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - xlnx,axi-fifo-mm-s-4.1
> +      - xlnx,axi-fifo-mm-s-4.2
> +      - xlnx,axi-fifo-mm-s-4.3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  xlnx,axi-str-rxd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Width of the receive AXI-Stream data bus in bits. Currently only 32
> +      is supported.
> +    const: 32
> +
> +  xlnx,axi-str-txd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Width of the transmit AXI-Stream data bus in bits. Currently only 32
> +      is supported.
> +    const: 32
> +
> +  xlnx,rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of the receive FIFO in words.
> +
> +  xlnx,tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of the transmit FIFO in words.
> +
> +  xlnx,use-rx-data:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Set to 1 if the receive data FIFO is enabled, 0 otherwise.
> +    enum: [0, 1]
> +
> +  xlnx,use-tx-data:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Set to 1 if the transmit data FIFO is enabled, 0 otherwise.
> +    enum: [0, 1]
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +  - xlnx,use-rx-data
> +  - xlnx,use-tx-data
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    axi_fifo: fifo@43c00000 {
> +        compatible = "xlnx,axi-fifo-mm-s-4.3";
> +        reg = <0x43c00000 0x10000>;
> +        interrupts = <0 30 4>;
> +        interrupt-parent = <&gic>;
> +        xlnx,axi-str-rxd-tdata-width = <32>;
> +        xlnx,axi-str-txd-tdata-width = <32>;
> +        xlnx,rx-fifo-depth = <0x1000>;
> +        xlnx,tx-fifo-depth = <0x1000>;
> +        xlnx,use-rx-data = <1>;
> +        xlnx,use-tx-data = <1>;
> +    };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9b107057ad8c..84be7c8ae257 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -29130,6 +29130,12 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
>  F:	drivers/net/ethernet/xilinx/xilinx_axienet*
>  
> +XILINX AXI-STREAM FIFO DRIVER
> +M:	Jacob Feder <jacobsfeder@gmail.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> +F:	drivers/staging/axis-fifo/
> +
>  XILINX CAN DRIVER
>  M:	Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
>  L:	linux-can@vger.kernel.org
> -- 
> 2.52.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]