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From: sashiko-bot@kernel.org
To: "Dmitry Baryshkov" <dmitry.baryshkov@oss.qualcomm.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
	krzk+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
Date: Thu, 14 May 2026 04:57:15 +0000	[thread overview]
Message-ID: <20260514045715.E22CCC2BCB7@smtp.kernel.org> (raw)
In-Reply-To: <20260513-iris-sc8280xp-v6-3-0d11d90d3e26@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The Venus/Iris driver ignores the `mmcx` power domain, failing to vote for its performance states which will cause MMCX under-voltage and AXI bus hangs at high clock speeds.
- [Low] The `power-domains` property in the `video-codec` node has 4 items, but the YAML binding `qcom,sm8250-venus.yaml` restricts it to a maximum of 3 items.
- [Low] The reserved memory node name 'pil_video_region@86700000' uses underscores instead of hyphens.
--

commit 436af127f4d0421fee1976f98a2eab9818c98aa4
Author: Konrad Dybcio <konradybcio@kernel.org>

arm64: dts: qcom: sc8280xp: Add Iris core

Add the required nodes to enable Iris core on SC8280XP.

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[ ... ]
@@ -691,6 +694,11 @@ reserved-region@85b00000 {
 			no-map;
 		};
 
> +		pil_video_mem: pil_video_region@86700000 {
> +			reg = <0 0x86700000 0 0x500000>;
> +			no-map;
> +		};
> +

This isn't a bug, but device tree conventions expect node names to use hyphens
instead of underscores. Should pil_video_region@86700000 be renamed to
pil-video-region@86700000 to avoid dtc W=1 warnings?

[ ... ]
@@ -4181,6 +4189,97 @@ usb_1_dwc3_ss: endpoint {
 			};
 		};
 
> +		iris: video-codec@aa00000 {
> +			compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
> +			reg = <0x0 0x0aa00000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> +			power-domains = <&videocc MVS0C_GDSC>,
> +					<&videocc MVS0_GDSC>,
> +					<&rpmhpd SC8280XP_MX>,
> +					<&rpmhpd SC8280XP_MMCX>;
> +			power-domain-names = "venus",
> +					     "vcodec0",
> +					     "mx",
> +					     "mmcx";

Does the YAML binding for qcom,sm8250-venus support 4 power domains?

Without adding a conditional block for qcom,sc8280xp-iris, won't this fail
dtbs_check since the fallback schema restricts power-domains to a maximum
of 3 items (venus, vcodec0, mx)?

Additionally, since this falls back to qcom,sm8250-venus, will the Venus
driver properly attach and vote for the mmcx power domain?

The video codec driver using sm8250 data explicitly defines only mx as the
OPP power domain. As a result, devm_pm_domain_attach_list() might only
attach mx and ignore mmcx.

If mmcx is ignored by the driver, won't it remain permanently at the lowest
statically configured state? When the codec dynamically scales to higher
frequencies (e.g., 560MHz) requiring turbo_l1 for mmcx, could this lead to
hardware under-voltage and AXI bus lockups?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-iris-sc8280xp-v6-0-0d11d90d3e26@oss.qualcomm.com?part=3

  reply	other threads:[~2026-05-14  4:57 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
2026-05-14  4:57   ` sashiko-bot [this message]
2026-05-13 12:34 ` [PATCH v6 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
2026-05-14  5:38   ` sashiko-bot
2026-05-13 12:34 ` [PATCH v6 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov

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