Re: [PATCH v3 5/7] clk: qcom: gpucc: Add GPU Clock Controller driver for Eliza

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardware State Conflict and CCF Reference Counting Race on SMMU Vote Clocks
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commit 677d8bac725b37e31762837245d464597c8a7f08
Author: Taniya Das <taniya.das@oss.qualcomm.com>

clk: qcom: gpucc: Add GPU Clock Controller driver for Eliza

This commit adds Graphics Clock Controller (GPUCC) support for the Eliza
platform.

> diff --git a/drivers/clk/qcom/gpucc-eliza.c b/drivers/clk/qcom/gpucc-eliza.c
> new file mode 100644
> index 0000000000000..85ae0ab118405
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-eliza.c

[ ... ]

> +static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
> +	.halt_reg = 0x7000,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x7000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gpu_cc_gpu_smmu_vote_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
> +	.halt_reg = 0x7000,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x7000,
> +		.enable_mask = BIT(0),

Will this cause a hardware state conflict?

Both gpu_cc_gpu_smmu_vote_clk and gpu_cc_hlos1_vote_gpu_smmu_clk are defined
using the exact same hardware register (0x7000) and mask (BIT(0)).

Since the Common Clock Framework maintains software reference counts per
clk_core instance rather than per hardware bit, if two separate consumers
enable these clocks, both will set BIT(0).

If one consumer then disables its clock, the disable callback will clear
BIT(0) in hardware because its local software reference count reached 0.
This would turn off the physical clock even though the other consumer's
reference count is still positive.

Could this lead to a system hang, bus fault, or unrecoverable kernel panic
when the active consumer accesses the unclocked hardware?

> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};

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Sashiko AI review · https://sashiko.dev/#/patchset/20260513-eliza_mm_cc_v2-v3-0-b59c370dc281@oss.qualcomm.com?part=5