Re: [PATCH v4 5/7] clk: qcom: gpucc: Add GPU Clock Controller driver for Eliza

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Duplicate clock definitions for the same hardware register and bit (gpu_cc_gpu_smmu_vote_clk and gpu_cc_hlos1_vote_gpu_smmu_clk).
--

commit 6d648a0e43468c77f650349682c80884c4151795
Author: Taniya Das <taniya.das@oss.qualcomm.com>

clk: qcom: gpucc: Add GPU Clock Controller driver for Eliza

This commit adds the Graphics Clock Controller (GPUCC) driver for the Eliza
platform, providing clock, reset, and GDSC definitions.

> diff --git a/drivers/clk/qcom/gpucc-eliza.c b/drivers/clk/qcom/gpucc-eliza.c
> new file mode 100644
> index 0000000000000..85ae0ab118405
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-eliza.c

[ ... ]

> +static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
> +	.halt_reg = 0x7000,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x7000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gpu_cc_gpu_smmu_vote_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
> +	.halt_reg = 0x7000,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x7000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};

Both gpu_cc_gpu_smmu_vote_clk and gpu_cc_hlos1_vote_gpu_smmu_clk map to the
exact same hardware register (0x7000) and enable mask (BIT(0)).

Because the Common Clock Framework maintains independent reference counts and
state for each clock object, if one consumer disables its clock, won't CCF
clear BIT(0) in register 0x7000?

Could this abruptly shut down the SMMU clock in hardware even if the other
consumer's reference count is still active?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com?part=5