* [PATCH 1/2] spi: dt-bindings: spi-qpic-snand: Add ipq5210 compatible
2026-05-14 6:45 [PATCH 0/2] Enable QPIC-SPI-NAND controller for ipq5210 Varadarajan Narayanan
@ 2026-05-14 6:45 ` Varadarajan Narayanan
2026-05-14 6:45 ` [PATCH 2/2] arm64: dts: qcom: ipq5210: Add QPIC SPI NAND controller support Varadarajan Narayanan
1 sibling, 0 replies; 4+ messages in thread
From: Varadarajan Narayanan @ 2026-05-14 6:45 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
sadre Alam, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-spi, devicetree, linux-kernel,
Varadarajan Narayanan
Since the QPIC-SPI-NAND flash controller present in ipq5210 is the same
as the one found in ipq9574, document the ipq5210 compatible and with
ipq9574 as the fallback.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
index 7d0571feb46d..829da22537d4 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
@@ -25,6 +25,7 @@ properties:
- items:
- enum:
- qcom,ipq5018-snand
+ - qcom,ipq5210-snand
- qcom,ipq5332-snand
- qcom,ipq5424-snand
- const: qcom,ipq9574-snand
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] arm64: dts: qcom: ipq5210: Add QPIC SPI NAND controller support
2026-05-14 6:45 [PATCH 0/2] Enable QPIC-SPI-NAND controller for ipq5210 Varadarajan Narayanan
2026-05-14 6:45 ` [PATCH 1/2] spi: dt-bindings: spi-qpic-snand: Add ipq5210 compatible Varadarajan Narayanan
@ 2026-05-14 6:45 ` Varadarajan Narayanan
2026-05-14 12:50 ` sashiko-bot
1 sibling, 1 reply; 4+ messages in thread
From: Varadarajan Narayanan @ 2026-05-14 6:45 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
sadre Alam, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, linux-spi, devicetree, linux-kernel,
Varadarajan Narayanan
Add device tree nodes for QPIC SPI NAND flash controller support on
ipq5210 SoC.
The ipq5210 SoC includes a QPIC controller that supports SPI NAND flash
devices with hardware ECC capabilities and DMA support through BAM (Bus
Access Manager).
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 42 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 29 ++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
index 941f866ecfe9..4813662c2d6c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
@@ -20,6 +20,25 @@ chosen {
};
};
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ pinctrl-0 = <&qpic_snand_default_state>;
+ pinctrl-names = "default";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-engine = <&qpic_nand>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ };
+};
+
&sdhc {
max-frequency = <192000000>;
bus-width = <4>;
@@ -36,6 +55,29 @@ &sleep_clk {
};
&tlmm {
+ qpic_snand_default_state: qpic-snand-default-state {
+ clock-pins {
+ pins = "gpio5";
+ function = "qspi_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio4";
+ function = "qspi_cs_n";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "qspi_data";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
qup_uart1_default_state: qup-uart1-default-state {
pins = "gpio38", "gpio39";
function = "qup_se1";
diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 3761eb03ab24..7fd4291caff2 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -204,6 +204,35 @@ sdhc: mmc@7804000 {
status = "disabled";
};
+ qpic_bam: dma-controller@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x07984000 0x0 0x1c000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: spi@79b0000 {
+ compatible = "qcom,ipq5210-snand", "qcom,ipq9574-snand";
+ reg = <0x0 0x079b0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>,
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
+ clock-names = "core", "aon", "iom";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread