[PATCH 0/2] add PIT DTS support for S32G2/S32G3 SoCs

[PATCH 0/2] add PIT DTS support for S32G2/S32G3 SoCs

[Khristine Andreea Barbulescu]

This patchset aims to add one change to the S32G2/S32G3 dtsi support:
- Add PIT dts support for S32G SoC based boards

Khristine Andreea Barbulescu (2):
  arm64: dts: s32g: add PIT support for s32g2 and s32g3
  dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

 .../bindings/timer/fsl,vf610-pit.yaml         |  8 ++++++++
 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 20 ++++++++++++++++++-
 arch/arm64/boot/dts/freescale/s32g3.dtsi      | 20 ++++++++++++++++++-
 3 files changed, 46 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/2] arm64: dts: s32g: add PIT support for s32g2 and s32g3

[Khristine Andreea Barbulescu]

Add PIT0 and PIT1 for S32G2 and S32G3 SoCs

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 +++++++++++++++++++-
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 +++++++++++++++++++-
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..57ff97e44507 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -417,6 +417,15 @@ edma0: dma-controller@40144000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit0: pit@40188000 {
+			compatible = "nxp,s32g2-pit";
+			reg = <0x40188000 0x3000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can0: can@401b4000 {
 			compatible = "nxp,s32g2-flexcan";
 			reg = <0x401b4000 0xa000>;
@@ -622,6 +631,15 @@ edma1: dma-controller@40244000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit1: pit@40288000 {
+			compatible = "nxp,s32g2-pit";
+			reg = <0x40288000 0x3000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can2: can@402a8000 {
 			compatible = "nxp,s32g2-flexcan";
 			reg = <0x402a8000 0xa000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..efe5398e1240 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
  *
  * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
  *          Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -475,6 +475,15 @@ edma0: dma-controller@40144000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit0: pit@40188000 {
+			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+			reg = <0x40188000 0x3000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can0: can@401b4000 {
 			compatible = "nxp,s32g3-flexcan",
 					   "nxp,s32g2-flexcan";
@@ -693,6 +702,15 @@ edma1: dma-controller@40244000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit1: pit@40288000 {
+			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+			reg = <0x40288000 0x3000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can2: can@402a8000 {
 			compatible = "nxp,s32g3-flexcan",
 					   "nxp,s32g2-flexcan";
-- 
2.34.1

[PATCH 2/2] dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

[Khristine Andreea Barbulescu]

Add devicetree binding example for the PIT timer as used on
NXP S32G2 and S32G3 platforms.

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
 .../devicetree/bindings/timer/fsl,vf610-pit.yaml          | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
index 42e130654d58..8696696776b3 100644
--- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
+++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
@@ -57,3 +57,11 @@ examples:
         clocks = <&clks VF610_CLK_PIT>;
         clock-names = "pit";
     };
+
+    pit@40188000 {
+        compatible = "nxp,s32g2-pit";
+        reg = <0x40188000 0x3000>;
+        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks 61>;
+        clock-names = "pit";
+    };
-- 
2.34.1

Re: [PATCH 1/2] arm64: dts: s32g: add PIT support for s32g2 and s32g3

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The Device Tree nodes for the PIT timers are named using the specific IP block name (`pit@...`) instead of the standard generic name (`timer@...`).
--

commit 427ff80913e8247c6a4011dd8722ce9a6b67e322
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

arm64: dts: s32g: add PIT support for s32g2 and s32g3

This commit adds Device Tree nodes for the Programmable Interrupt Timer
(PIT0 and PIT1) blocks on S32G2 and S32G3 SoCs.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi

[ ... ]

> @@ -417,6 +417,15 @@ edma0: dma-controller@40144000 {
>  			clock-names = "dmamux0", "dmamux1";
>  		};
>  
> +		pit0: pit@40188000 {

This isn't a bug, but according to the Devicetree Specification (Section
2.2.2 "Generic Names Recommendation"), node names should reflect the
generic function of the device rather than the specific IP block.

Could this node, as well as the pit1 node and the equivalent nodes in
s32g3.dtsi, be named timer@... instead of pit@... to follow standard
Device Tree conventions?

> +			compatible = "nxp,s32g2-pit";
> +			reg = <0x40188000 0x3000>;
> +			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 61>;
> +			clock-names = "pit";
> +			status = "disabled";
> +		};
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260514070605.996462-1-khristineandreea.barbulescu@oss.nxp.com?part=1

Re: [PATCH 2/2] dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Incorrect Interrupt Cells Representation in DT Example
- [Low] Non-Generic Device Tree Node Name
- [Low] Example Scope Confusion and Structural Redundancy
--

commit 0c9d62d6961d94621407fcbe8691b419e9baf7f8
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

This commit adds a devicetree binding example for the PIT timer
as used on nxp s32g2 and s32g3 platforms.

> diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
[ ... ]
> @@ -57,3 +57,11 @@ examples:
>          clocks = <&clks VF610_CLK_PIT>;
>          clock-names = "pit";
>      };
> +
> +    pit@40188000 {

This isn't a bug, but the devicetree specification mandates generic node
names reflecting the function of the device. Should this be named
timer@40188000 instead of pit@40188000?

> +        compatible = "nxp,s32g2-pit";
> +        reg = <0x40188000 0x3000>;
> +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;

Since the nxp s32g2 platform is an arm64 soc using the arm generic interrupt
controller (gicv3), doesn't it require a 3-cell interrupt specifier (such as
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>)?

Will this 2-cell representation cause dtc compilation errors or misrepresent
the physical hardware routing for users copying the example?

> +        clocks = <&clks 61>;
> +        clock-names = "pit";
> +    };

This isn't a bug, but adding this to the exact same yaml list item as the
existing vf610 timer example causes the schema compiler to interpret them as
existing simultaneously within the same root device tree. 

Since they share the exact same property structure, is a separate example
for this platform strictly necessary, or could it just cause structural
redundancy and bloat the schema?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260514070605.996462-1-khristineandreea.barbulescu@oss.nxp.com?part=2

Re: [PATCH 2/2] dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1234 bytes --]

On Thu, May 14, 2026 at 09:06:05AM +0200, Khristine Andreea Barbulescu wrote:
> Add devicetree binding example for the PIT timer as used on
> NXP S32G2 and S32G3 platforms.
> 
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

This doesn't add anything to the binding of value, all properties appear
the same as the existing example?
pw-bot: rejected

Cheers,
Conor.

> ---
>  .../devicetree/bindings/timer/fsl,vf610-pit.yaml          | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> index 42e130654d58..8696696776b3 100644
> --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> @@ -57,3 +57,11 @@ examples:
>          clocks = <&clks VF610_CLK_PIT>;
>          clock-names = "pit";
>      };
> +
> +    pit@40188000 {
> +        compatible = "nxp,s32g2-pit";
> +        reg = <0x40188000 0x3000>;
> +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clks 61>;
> +        clock-names = "pit";
> +    };
> -- 
> 2.34.1
> 

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Re: [PATCH 2/2] dt-bindings: timer: pit: add PIT node example for s32g2/3 platforms

[Frank Li]

On Thu, May 14, 2026 at 09:06:05AM +0200, Khristine Andreea Barbulescu wrote:
> Add devicetree binding example for the PIT timer as used on
> NXP S32G2 and S32G3 platforms.
>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
> ---
>  .../devicetree/bindings/timer/fsl,vf610-pit.yaml          | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> index 42e130654d58..8696696776b3 100644
> --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml
> @@ -57,3 +57,11 @@ examples:
>          clocks = <&clks VF610_CLK_PIT>;
>          clock-names = "pit";
>      };
> +
> +    pit@40188000 {
> +        compatible = "nxp,s32g2-pit";
> +        reg = <0x40188000 0x3000>;
> +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clks 61>;
> +        clock-names = "pit";
> +    };

Needn't change example

Frank
> --
> 2.34.1
>