Re: [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing dma-coherent property on other SMMU clients causes data corruption
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commit be9ce7db4922ed7d48488efa182130301cfa9435
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

The commit asserts that SMMU transactions are cache coherent and adds
dma-coherent to the XGMAC nodes. This prevents redundant cache flush and
invalidate operations and potential stale data issues.

> The SMMU is enabled and transactions going through it are cache
> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
> redundant cache flush/invalidate operations and potential stale data
> issues.

This problem wasn't introduced by this patch, but the patch provides an
incomplete fix.

The commit message asserts that "transactions going through it are cache
coherent" and correctly notes that missing the dma-coherent property causes
"potential stale data issues".

On ARM64, if a hardware-coherent device is treated as non-coherent, the kernel
will execute cache invalidation (dcache_inval_poc -> dc ivac via
arch_sync_dma_for_cpu) for DMA_FROM_DEVICE transfers.

If the device wrote data directly into the CPU caches, the dc ivac instruction
will discard those dirty cache lines without writing them back to RAM. This
destroys the DMA writes and causes the CPU to read stale data from memory,
resulting in reproducible data corruption.

If the SMMU provides coherency for all transactions, do other major DMA
masters that also route through the SMMU need the dma-coherent property?

For example, usb0, dmac0, and dmac1 use the SMMU but lack the property:

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi:
    usb0: usb@10b00000 {
        ...
        iommus = <&smmu 6>;
        ...
    };

    dmac0: dma-controller@0 {
        ...
        iommus = <&smmu 8>;
        ...
    };

    dmac1: dma-controller@10000 {
        ...
        iommus = <&smmu 9>;
        ...
    };

If coherency is specific only to XGMAC, could the commit message be clarified
to avoid a blanket statement about the SMMU?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2