* [PATCH v2 0/3] memory: tegra264: Add full set of MC clients
@ 2026-05-18 12:43 Sumit Gupta
2026-05-18 12:43 ` [PATCH v2 1/3] memory: tegra264: Skip clients without bpmp_id or type Sumit Gupta
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Sumit Gupta @ 2026-05-18 12:43 UTC (permalink / raw)
To: krzk, treding, jonathanh, robh, conor+dt, linux-kernel,
linux-tegra, devicetree
Cc: bbasu, sumitg
Extend the Tegra264 MC dt-bindings header and tegra264_mc_clients[]
table to cover the full set of memory clients exposed by the SoC.
---
v1[1] -> v2:
- patch 1 (new): skip ICC requests if no .bpmp_id or .type.
- patch 2 (new): split dt-bindings into a separate patch.
- patch 3: update commit message to reflect entries sorted by SID
override/security register offsets (same as previous SoCs).
Sumit Gupta (3):
memory: tegra264: Skip clients without bpmp_id or type
dt-bindings: memory: tegra264: Add full set of MC client IDs
memory: tegra264: Add full set of MC clients
drivers/memory/tegra/tegra264.c | 568 +++++++++++++++++--
include/dt-bindings/memory/nvidia,tegra264.h | 287 ++++++++++
2 files changed, 823 insertions(+), 32 deletions(-)
[1] https://lore.kernel.org/lkml/20260515171911.1929868-1-sumitg@nvidia.com/
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/3] memory: tegra264: Skip clients without bpmp_id or type 2026-05-18 12:43 [PATCH v2 0/3] memory: tegra264: Add full set of MC clients Sumit Gupta @ 2026-05-18 12:43 ` Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 3/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2 siblings, 0 replies; 8+ messages in thread From: Sumit Gupta @ 2026-05-18 12:43 UTC (permalink / raw) To: krzk, treding, jonathanh, robh, conor+dt, linux-kernel, linux-tegra, devicetree Cc: bbasu, sumitg Some MC clients are present in tegra264_mc_clients[] only for fault-log naming and have no .bpmp_id or .type assigned. Skip forwarding bandwidth requests to BPMP for such clients in tegra264_mc_icc_set(). Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra264.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra264.c index e43ef14da1ee..e62890841725 100644 --- a/drivers/memory/tegra/tegra264.c +++ b/drivers/memory/tegra/tegra264.c @@ -262,6 +262,10 @@ static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst) return -ENOENT; } + /* Skip forwarding bw requests to BPMP from clients without bpmp_id/type. */ + if (pclient->type == TEGRA_ICC_NONE || !pclient->bpmp_id) + return 0; + if (pclient->type == TEGRA_ICC_NISO) bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; else -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs 2026-05-18 12:43 [PATCH v2 0/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 1/3] memory: tegra264: Skip clients without bpmp_id or type Sumit Gupta @ 2026-05-18 12:43 ` Sumit Gupta 2026-05-18 13:10 ` sashiko-bot 2026-05-18 12:43 ` [PATCH v2 3/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2 siblings, 1 reply; 8+ messages in thread From: Sumit Gupta @ 2026-05-18 12:43 UTC (permalink / raw) To: krzk, treding, jonathanh, robh, conor+dt, linux-kernel, linux-tegra, devicetree Cc: bbasu, sumitg Add the complete set of TEGRA264_MEMORY_CLIENT_* IDs exposed by the Tegra264 MC. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- include/dt-bindings/memory/nvidia,tegra264.h | 287 +++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h index 521405c01f84..c65403a76413 100644 --- a/include/dt-bindings/memory/nvidia,tegra264.h +++ b/include/dt-bindings/memory/nvidia,tegra264.h @@ -58,24 +58,108 @@ * memory client IDs */ +/* PTW read client mapped to SOC SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_PTCR 0x00 /* HOST1X read client */ #define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16 +#define TEGRA264_MEMORY_CLIENT_MPCORER 0x27 +/* Platform security (PSC) Read clients */ +#define TEGRA264_MEMORY_CLIENT_PSCR 0x33 +/* PSC Write clients */ +#define TEGRA264_MEMORY_CLIENT_PSCW 0x34 +/* ISP0 Read client */ +#define TEGRA264_MEMORY_CLIENT_ISP0R 0x37 +#define TEGRA264_MEMORY_CLIENT_MPCOREW 0x39 +/* ISP0 Write client */ +#define TEGRA264_MEMORY_CLIENT_ISP0W 0x44 +/* ISP1 Write client */ +#define TEGRA264_MEMORY_CLIENT_ISP1W 0x45 +/* ISP FALCON Read client */ +#define TEGRA264_MEMORY_CLIENT_ISPFALCONR 0x47 +/* ISP FALCON Write client */ +#define TEGRA264_MEMORY_CLIENT_ISPFALCONW 0x4f +/* MGBE2 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE2R 0x5c +#define TEGRA264_MEMORY_CLIENT_OFAR2MC 0x5d +#define TEGRA264_MEMORY_CLIENT_OFAW2MC 0x5e +/* MGBE2 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE2W 0x5f +/* MGBE3 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE3R 0x61 +/* MGBE3 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE3W 0x65 +/* SEU1 Memory Read Client */ +#define TEGRA264_MEMORY_CLIENT_SEU1RD 0x68 +/* SEU1 Memory Write Client */ +#define TEGRA264_MEMORY_CLIENT_SEU1WR 0x69 /* VIC read client */ #define TEGRA264_MEMORY_CLIENT_VICR 0x6c /* VIC Write client */ #define TEGRA264_MEMORY_CLIENT_VICW 0x6d /* VI R5 Write client */ #define TEGRA264_MEMORY_CLIENT_VIW 0x72 +/* QSPI Read Client */ +#define TEGRA264_MEMORY_CLIENT_XSPI0R 0x75 +/* QSPI Write Client */ +#define TEGRA264_MEMORY_CLIENT_XSPI0W 0x76 #define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78 #define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79 /* Audio processor(APE) Read client */ #define TEGRA264_MEMORY_CLIENT_APER 0x7a /* Audio processor(APE) Write client */ #define TEGRA264_MEMORY_CLIENT_APEW 0x7b +/* SEU0 read client */ +#define TEGRA264_MEMORY_CLIENT_SER 0x80 +/* SEU0 write client */ +#define TEGRA264_MEMORY_CLIENT_SEW 0x81 +/* AXI AP and DFD/Coresight1-AUX0/1 Read clients both share the same interface on MSS */ +#define TEGRA264_MEMORY_CLIENT_AXIAPR 0x82 +/* AXI AP and DFD/Coresight1-AUX0/1 Write clients both share the same interface on MSS */ +#define TEGRA264_MEMORY_CLIENT_AXIAPW 0x83 +/* ETR or DFD/Coresight0 Read Client */ +#define TEGRA264_MEMORY_CLIENT_ETRR 0x84 +/* ETR or DFD/Coresight0 Write Client */ +#define TEGRA264_MEMORY_CLIENT_ETRW 0x85 +/* Security(tsec) Read client */ +#define TEGRA264_MEMORY_CLIENT_TSECR 0x86 +/* Security(tsec) Write client */ +#define TEGRA264_MEMORY_CLIENT_TSECW 0x87 +/* BPMP read client */ +#define TEGRA264_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA264_MEMORY_CLIENT_BPMPW 0x94 +/* AON Read Client */ +#define TEGRA264_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA264_MEMORY_CLIENT_AONW 0x98 +/* GPCDMA debug Read client */ +#define TEGRA264_MEMORY_CLIENT_GPCDMAR 0x99 +/* GPCDMA debug Write client */ +#define TEGRA264_MEMORY_CLIENT_GPCDMAW 0x9a /* Audio DMA Read client */ #define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f /* Audio DMA Write client */ #define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0 +/* mss internal memqual MIU0 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU0R 0xa6 +/* mss internal memqual MIU0 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU0W 0xa7 +/* mss internal memqual MIU1 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU1R 0xa8 +/* mss internal memqual MIU1 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU1W 0xa9 +/* mss internal memqual MIU2 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU2R 0xae +/* mss internal memqual MIU2 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU2W 0xaf +/* mss internal memqual MIU3 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU3R 0xb0 +/* mss internal memqual MIU3 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU3W 0xb1 +/* mss internal memqual MIU4 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU4R 0xb2 +/* mss internal memqual MIU4 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU4W 0xb3 #define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6 #define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7 /* VI Falcon Read client */ @@ -86,6 +170,8 @@ #define TEGRA264_MEMORY_CLIENT_RCER 0xd2 /* Write client of RCE */ #define TEGRA264_MEMORY_CLIENT_RCEW 0xd3 +#define TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC 0xd6 +#define TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC 0xd7 /* PCIE0/MSI Write clients */ #define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9 /* PCIE1/RPX4 Read clients */ @@ -108,16 +194,140 @@ #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 /* PCIE5/DMX4 Write clients */ #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 +/* mss internal memqual MIU5 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU5R 0xfc +/* mss internal memqual MIU5 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU5W 0xfd +/* mss internal memqual MIU6 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU6W 0xff +#define TEGRA264_MEMORY_CLIENT_RISTR 0x100 +#define TEGRA264_MEMORY_CLIENT_RISTW 0x101 +/* OESP (Pluton) Read client */ +#define TEGRA264_MEMORY_CLIENT_OESPR 0x102 +/* OESP (Pluton) Write client */ +#define TEGRA264_MEMORY_CLIENT_OESPW 0x103 +/* mss internal memqual MIU7 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU7W 0x105 +/* mss internal memqual MIU8 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU8R 0x106 +/* mss internal memqual MIU8 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU8W 0x107 +/* mss internal memqual MIU9 reads */ +#define TEGRA264_MEMORY_CLIENT_MIU9R 0x108 +/* mss internal memqual MIU9 writes */ +#define TEGRA264_MEMORY_CLIENT_MIU9W 0x109 +/* HWPM Write Interface */ +#define TEGRA264_MEMORY_CLIENT_PMA0AWR 0x122 +#define TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC 0x123 +#define TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC 0x124 +/* CTW read client mapped to SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_SMMU0CTWR 0x12e +/* CMDQV read client mapped to SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR 0x12f +/* CMDQV write client mapped to SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW 0x130 +/* EVNTQ write client mapped to SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW 0x131 +/* PTW read client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1PTWR 0x132 +/* CTW read client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1CTWR 0x134 +/* CMDQV read client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR 0x135 +/* CMDQV write client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW 0x136 +/* EVNTQ write client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW 0x137 +/* PTW read client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2PTWR 0x138 +/* CTW read client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2CTWR 0x13a +/* CMDQV read client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR 0x13b +/* CMDQV write client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW 0x13c +/* EVNTQ write client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW 0x13d +/* CMDQ read client mapped to SMMU0 */ +#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQR 0x144 +/* CMDQ read client mapped to SMMU1 */ +#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQR 0x145 +/* CMDQ read client mapped to SMMU2 */ +#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQR 0x146 +/* Audio processor1(APE1) Read client */ +#define TEGRA264_MEMORY_CLIENT_APE1R 0x150 +/* Audio processor1(APE1) Write client */ +#define TEGRA264_MEMORY_CLIENT_APE1W 0x151 /* UFS Read client */ #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c /* UFS write client */ #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d +/* XUSB HOST Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166 +/* XUSB HOST Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167 +/* XUSB SS0 Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168 +/* XUSB SS1 Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169 +/* XUSB SS2 Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3R 0x16a +/* XUSB SS2 Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3W 0x16b +/* XUSB SS3 Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4R 0x16c +/* XUSB SS3 Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4W 0x16d +/* XUSB DEV Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5R 0x16e +/* XUSB DEV Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5W 0x16f +/* DCE Read client */ +#define TEGRA264_MEMORY_CLIENT_DCER 0x17a +/* DCE Write client */ +#define TEGRA264_MEMORY_CLIENT_DCEW 0x17b /* HDA Read client */ #define TEGRA264_MEMORY_CLIENT_HDAR 0x17c /* HDA Write client */ #define TEGRA264_MEMORY_CLIENT_HDAW 0x17d +/* DISPNISO read client */ +#define TEGRA264_MEMORY_CLIENT_DISPNISOR 0x17e +/* DISPNISO write client */ +#define TEGRA264_MEMORY_CLIENT_DISPNISOW 0x17f +/* XUSB SS0 Write Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1W 0x180 +/* XUSB SS1 Read Client */ +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2R 0x181 /* Disp ISO Read Client */ #define TEGRA264_MEMORY_CLIENT_DISPR 0x182 +/* MSSSEQ Read Client */ +#define TEGRA264_MEMORY_CLIENT_MSSSEQR 0x185 +/* MSSSEQ Write Client */ +#define TEGRA264_MEMORY_CLIENT_MSSSEQW 0x186 +/* PTW read client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3PTWR 0x18b +/* CTW read client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3CTWR 0x18d +/* CMDQV read client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR 0x18e +/* CMDQV write client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW 0x18f +/* EVNTQ write client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW 0x190 +/* CMDQ read client mapped to SMMU3 */ +#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQR 0x191 +/* PTW read client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4PTWR 0x192 +/* CTW read client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4CTWR 0x194 +/* CMDQV read client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR 0x195 +/* CMDQV write client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW 0x196 +/* EVNTQ write client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW 0x197 +/* CMDQ read client mapped to SMMU4 */ +#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQR 0x198 /* MGBE0 Read mccif */ #define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2 /* MGBE0 Write mccif */ @@ -128,9 +338,86 @@ #define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5 /* VI1 R5 Write client */ #define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6 +/* VI Falcon1 Read client */ +#define TEGRA264_MEMORY_CLIENT_VIFALCON1R 0x1a7 +/* VI Falcon1 Write client */ +#define TEGRA264_MEMORY_CLIENT_VIFALCON1W 0x1a8 +/* ISP FALCON1 Read client */ +#define TEGRA264_MEMORY_CLIENT_ISPFALCON1R 0x1a9 +/* ISP FALCON1 Write client */ +#define TEGRA264_MEMORY_CLIENT_ISPFALCON1W 0x1aa +/* Read Client of RCE1 */ +#define TEGRA264_MEMORY_CLIENT_RCE1R 0x1ab +/* Write client of RCE1 */ +#define TEGRA264_MEMORY_CLIENT_RCE1W 0x1ac +/* SEU2 Read client */ +#define TEGRA264_MEMORY_CLIENT_SEU2R 0x1ad +/* SEU2 Write client */ +#define TEGRA264_MEMORY_CLIENT_SEU2W 0x1ae +/* SEU3 Read client */ +#define TEGRA264_MEMORY_CLIENT_SEU3R 0x1af +/* SEU3 Write client */ +#define TEGRA264_MEMORY_CLIENT_SEU3W 0x1b0 +/* PVA0 Falcon Read mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA0R 0x1b1 +/* PVA0 Falcon Write mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA0W 0x1b2 +/* PVA1 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA1R 0x1b3 +/* PVA1 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA1W 0x1b4 +/* PVA2 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA2R 0x1b5 +/* PVA2 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_PVA2W 0x1b6 +/* ISP3 Write client */ +#define TEGRA264_MEMORY_CLIENT_ISP3W 0x1b7 +/* ISP2 Read Client */ +#define TEGRA264_MEMORY_CLIENT_ISP2R 0x1b8 +/* ISP2 Write Client */ +#define TEGRA264_MEMORY_CLIENT_ISP2W 0x1b9 +/* EQOS Read mccif */ +#define TEGRA264_MEMORY_CLIENT_EQOSR 0x1bc +/* EQOS Write mccif */ +#define TEGRA264_MEMORY_CLIENT_EQOSW 0x1bd +/* FSI0 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_FSI0R 0x1be +/* FSI0 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_FSI0W 0x1bf +/* FSI1 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_FSI1R 0x1c0 +/* FSI1 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_FSI1W 0x1c1 /* SDMMC0 Read mccif */ #define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2 /* SDMMC0 Write mccif */ #define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3 +/* Strongbox (SB) read client */ +#define TEGRA264_MEMORY_CLIENT_SBR 0x1c6 +/* Strongbox (SB) write client */ +#define TEGRA264_MEMORY_CLIENT_SBW 0x1c7 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU0R 0x1c8 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU0W 0x1c9 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU1R 0x1ca +#define TEGRA264_MEMORY_CLIENT_HSS_MIU1W 0x1cb +#define TEGRA264_MEMORY_CLIENT_HSS_MIU2R 0x1cc +#define TEGRA264_MEMORY_CLIENT_HSS_MIU2W 0x1cd +#define TEGRA264_MEMORY_CLIENT_HSS_MIU3R 0x1ce +#define TEGRA264_MEMORY_CLIENT_HSS_MIU3W 0x1cf +#define TEGRA264_MEMORY_CLIENT_HSS_MIU4R 0x1d0 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU4W 0x1d1 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU5R 0x1d2 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU5W 0x1d3 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU6R 0x1d4 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU6W 0x1d5 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU7R 0x1d6 +#define TEGRA264_MEMORY_CLIENT_HSS_MIU7W 0x1d7 +#define TEGRA264_MEMORY_CLIENT_GMMUR2MC 0x1d8 +#define TEGRA264_MEMORY_CLIENT_UCFELAR 0x1d9 +#define TEGRA264_MEMORY_CLIENT_UCFELAW 0x1da +#define TEGRA264_MEMORY_CLIENT_SLCR 0x1db +#define TEGRA264_MEMORY_CLIENT_SLCW 0x1dc +#define TEGRA264_MEMORY_CLIENT_REMOTER 0x1dd +#define TEGRA264_MEMORY_CLIENT_REMOTEW 0x1de #endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs 2026-05-18 12:43 ` [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs Sumit Gupta @ 2026-05-18 13:10 ` sashiko-bot 2026-05-18 17:51 ` Sumit Gupta 0 siblings, 1 reply; 8+ messages in thread From: sashiko-bot @ 2026-05-18 13:10 UTC (permalink / raw) To: Sumit Gupta; +Cc: conor+dt, robh, devicetree Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The macros for the XUSB HOST memory clients are incorrectly named as `XUSB_DEV`. -- commit f7f5816878d7a2d26ed25199c9ab18008b75aa76 Author: Sumit Gupta <sumitg@nvidia.com> dt-bindings: memory: tegra264: Add full set of MC client IDs This commit adds the complete set of TEGRA264_MEMORY_CLIENT_* IDs exposed by the Tegra264 memory controller. > diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h > index 521405c01f84c..c65403a764134 100644 > --- a/include/dt-bindings/memory/nvidia,tegra264.h > +++ b/include/dt-bindings/memory/nvidia,tegra264.h [ ... ] > @@ -108,16 +194,140 @@ > #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 > /* PCIE5/DMX4 Write clients */ > #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 [ ... ] > /* UFS Read client */ > #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c > /* UFS write client */ > #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d > +/* XUSB HOST Read Client */ > +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166 > +/* XUSB HOST Write Client */ > +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167 Should these macros be named TEGRA264_MEMORY_CLIENT_XUSB_HOSTR and TEGRA264_MEMORY_CLIENT_XUSB_HOSTW instead? The inline comments document them as XUSB HOST clients, but the macro names use DEV. Previous Tegra generations typically separate the host and device endpoints using HOSTR/HOSTW and DEVR/DEVW. Since device tree bindings constitute public ABI, could using DEV for the host endpoints cause confusion for future drivers mapping the interconnect paths? > +/* XUSB SS0 Read Client */ > +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168 > +/* XUSB SS1 Write Client */ > +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169 [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/20260518124306.2071481-1-sumitg@nvidia.com?part=2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs 2026-05-18 13:10 ` sashiko-bot @ 2026-05-18 17:51 ` Sumit Gupta 0 siblings, 0 replies; 8+ messages in thread From: Sumit Gupta @ 2026-05-18 17:51 UTC (permalink / raw) To: sashiko-reviews; +Cc: conor+dt, robh, devicetree, sumitg On 18/05/26 18:40, sashiko-bot@kernel.org wrote: > External email: Use caution opening links or attachments > > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] The macros for the XUSB HOST memory clients are incorrectly named as `XUSB_DEV`. > -- The XUSB_DEV* macro names match the header released by the BPMP-FW team. Keeping the delta minimal with the BPMP-FW header to avoid breaking ABI compatibility. Thank you, Sumit Gupta > > commit f7f5816878d7a2d26ed25199c9ab18008b75aa76 > Author: Sumit Gupta <sumitg@nvidia.com> > > dt-bindings: memory: tegra264: Add full set of MC client IDs > > This commit adds the complete set of TEGRA264_MEMORY_CLIENT_* IDs > exposed by the Tegra264 memory controller. > >> diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h >> index 521405c01f84c..c65403a764134 100644 >> --- a/include/dt-bindings/memory/nvidia,tegra264.h >> +++ b/include/dt-bindings/memory/nvidia,tegra264.h > [ ... ] >> @@ -108,16 +194,140 @@ >> #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 >> /* PCIE5/DMX4 Write clients */ >> #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 > [ ... ] >> /* UFS Read client */ >> #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c >> /* UFS write client */ >> #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d >> +/* XUSB HOST Read Client */ >> +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166 >> +/* XUSB HOST Write Client */ >> +#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167 > Should these macros be named TEGRA264_MEMORY_CLIENT_XUSB_HOSTR and > TEGRA264_MEMORY_CLIENT_XUSB_HOSTW instead? > > The inline comments document them as XUSB HOST clients, but the macro names > use DEV. Previous Tegra generations typically separate the host and device > endpoints using HOSTR/HOSTW and DEVR/DEVW. > > Since device tree bindings constitute public ABI, could using DEV for the > host endpoints cause confusion for future drivers mapping the interconnect > paths? > >> +/* XUSB SS0 Read Client */ >> +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168 >> +/* XUSB SS1 Write Client */ >> +#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169 > [ ... ] > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260518124306.2071481-1-sumitg@nvidia.com?part=2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] memory: tegra264: Add full set of MC clients 2026-05-18 12:43 [PATCH v2 0/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 1/3] memory: tegra264: Skip clients without bpmp_id or type Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs Sumit Gupta @ 2026-05-18 12:43 ` Sumit Gupta 2026-05-18 13:33 ` sashiko-bot 2 siblings, 1 reply; 8+ messages in thread From: Sumit Gupta @ 2026-05-18 12:43 UTC (permalink / raw) To: krzk, treding, jonathanh, robh, conor+dt, linux-kernel, linux-tegra, devicetree Cc: bbasu, sumitg Extend the tegra264_mc_clients table to cover the full set of memory clients exposed by the SoC. The client name is used for MC fault reporting. Clients managed by the BPMP bandwidth manager additionally carry their bpmp_id and type. Entries in tegra264_mc_clients[] are sorted to match the order of the override and security register offsets used in previous SoCs. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra264.c | 564 ++++++++++++++++++++++++++++++-- 1 file changed, 532 insertions(+), 32 deletions(-) diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra264.c index e62890841725..b8d6c4ce4836 100644 --- a/drivers/memory/tegra/tegra264.c +++ b/drivers/memory/tegra/tegra264.c @@ -21,45 +21,62 @@ */ static const struct tegra_mc_client tegra264_mc_clients[] = { { - .id = TEGRA264_MEMORY_CLIENT_HDAR, - .name = "hdar", - .bpmp_id = TEGRA264_BWMGR_HDA, - .type = TEGRA_ICC_ISO_AUDIO, + .id = TEGRA264_MEMORY_CLIENT_PTCR, + .name = "ptcr", }, { - .id = TEGRA264_MEMORY_CLIENT_HDAW, - .name = "hdaw", - .bpmp_id = TEGRA264_BWMGR_HDA, - .type = TEGRA_ICC_ISO_AUDIO, + .id = TEGRA264_MEMORY_CLIENT_HOST1XR, + .name = "host1xr", }, { - .id = TEGRA264_MEMORY_CLIENT_MGBE0R, - .name = "mgbe0r", - .bpmp_id = TEGRA264_BWMGR_EQOS, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_MPCORER, + .name = "mpcorer", }, { - .id = TEGRA264_MEMORY_CLIENT_MGBE0W, - .name = "mgbe0w", - .bpmp_id = TEGRA264_BWMGR_EQOS, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_PSCR, + .name = "pscr", }, { - .id = TEGRA264_MEMORY_CLIENT_MGBE1R, - .name = "mgbe1r", - .bpmp_id = TEGRA264_BWMGR_EQOS, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_PSCW, + .name = "pscw", }, { - .id = TEGRA264_MEMORY_CLIENT_MGBE1W, - .name = "mgbe1w", - .bpmp_id = TEGRA264_BWMGR_EQOS, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_ISP0R, + .name = "isp0r", }, { - .id = TEGRA264_MEMORY_CLIENT_SDMMC0R, - .name = "sdmmc0r", - .bpmp_id = TEGRA264_BWMGR_SDMMC_1, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_MPCOREW, + .name = "mpcorew", }, { - .id = TEGRA264_MEMORY_CLIENT_SDMMC0W, - .name = "sdmmc0w", - .bpmp_id = TEGRA264_BWMGR_SDMMC_1, - .type = TEGRA_ICC_NISO, + .id = TEGRA264_MEMORY_CLIENT_ISP0W, + .name = "isp0w", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISP1W, + .name = "isp1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISPFALCONR, + .name = "ispfalconr", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISPFALCONW, + .name = "ispfalconw", + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE2R, + .name = "mgbe2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_OFAR2MC, + .name = "ofar2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_OFAW2MC, + .name = "ofaw2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE2W, + .name = "mgbe2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE3R, + .name = "mgbe3r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE3W, + .name = "mgbe3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU1RD, + .name = "seu1rd", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU1WR, + .name = "seu1wr", }, { .id = TEGRA264_MEMORY_CLIENT_VICR, .name = "vicr", @@ -70,6 +87,15 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { .name = "vicw", .bpmp_id = TEGRA264_BWMGR_VIC, .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_VIW, + .name = "viw", + }, { + .id = TEGRA264_MEMORY_CLIENT_XSPI0R, + .name = "xspi0r", + }, { + .id = TEGRA264_MEMORY_CLIENT_XSPI0W, + .name = "xspi0w", }, { .id = TEGRA264_MEMORY_CLIENT_APER, .name = "aper", @@ -80,6 +106,48 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { .name = "apew", .bpmp_id = TEGRA264_BWMGR_APE, .type = TEGRA_ICC_ISO_AUDIO, + }, { + .id = TEGRA264_MEMORY_CLIENT_SER, + .name = "ser", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEW, + .name = "sew", + }, { + .id = TEGRA264_MEMORY_CLIENT_AXIAPR, + .name = "axiapr", + }, { + .id = TEGRA264_MEMORY_CLIENT_AXIAPW, + .name = "axiapw", + }, { + .id = TEGRA264_MEMORY_CLIENT_ETRR, + .name = "etrr", + }, { + .id = TEGRA264_MEMORY_CLIENT_ETRW, + .name = "etrw", + }, { + .id = TEGRA264_MEMORY_CLIENT_TSECR, + .name = "tsecr", + }, { + .id = TEGRA264_MEMORY_CLIENT_TSECW, + .name = "tsecw", + }, { + .id = TEGRA264_MEMORY_CLIENT_BPMPR, + .name = "bpmpr", + }, { + .id = TEGRA264_MEMORY_CLIENT_BPMPW, + .name = "bpmpw", + }, { + .id = TEGRA264_MEMORY_CLIENT_AONR, + .name = "aonr", + }, { + .id = TEGRA264_MEMORY_CLIENT_AONW, + .name = "aonw", + }, { + .id = TEGRA264_MEMORY_CLIENT_GPCDMAR, + .name = "gpcdmar", + }, { + .id = TEGRA264_MEMORY_CLIENT_GPCDMAW, + .name = "gpcdmaw", }, { .id = TEGRA264_MEMORY_CLIENT_APEDMAR, .name = "apedmar", @@ -90,6 +158,36 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { .name = "apedmaw", .bpmp_id = TEGRA264_BWMGR_APEDMA, .type = TEGRA_ICC_ISO_AUDIO, + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU0R, + .name = "miu0r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU0W, + .name = "miu0w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU1R, + .name = "miu1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU1W, + .name = "miu1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU2R, + .name = "miu2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU2W, + .name = "miu2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU3R, + .name = "miu3r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU3W, + .name = "miu3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU4R, + .name = "miu4r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU4W, + .name = "miu4w", }, { .id = TEGRA264_MEMORY_CLIENT_VIFALCONR, .name = "vifalconr", @@ -110,6 +208,12 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { .name = "rcew", .bpmp_id = TEGRA264_BWMGR_RCE, .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC, + .name = "nvenc1srd2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC, + .name = "nvenc1swr2mc", }, { .id = TEGRA264_MEMORY_CLIENT_PCIE0W, .name = "pcie0w", @@ -185,6 +289,402 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { .name = "nvdecswr2mc", .bpmp_id = TEGRA264_BWMGR_NVDEC, .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU5R, + .name = "miu5r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU5W, + .name = "miu5w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU6W, + .name = "miu6w", + }, { + .id = TEGRA264_MEMORY_CLIENT_RISTR, + .name = "ristr", + }, { + .id = TEGRA264_MEMORY_CLIENT_RISTW, + .name = "ristw", + }, { + .id = TEGRA264_MEMORY_CLIENT_OESPR, + .name = "oespr", + }, { + .id = TEGRA264_MEMORY_CLIENT_OESPW, + .name = "oespw", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU7W, + .name = "miu7w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU8R, + .name = "miu8r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU8W, + .name = "miu8w", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU9R, + .name = "miu9r", + }, { + .id = TEGRA264_MEMORY_CLIENT_MIU9W, + .name = "miu9w", + }, { + .id = TEGRA264_MEMORY_CLIENT_PMA0AWR, + .name = "pma0awr", + }, { + .id = TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC, + .name = "nvjpg1srd2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC, + .name = "nvjpg1swr2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU0CTWR, + .name = "smmu0ctwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR, + .name = "smmu0cmdqvr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW, + .name = "smmu0cmdqvw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW, + .name = "smmu0evntqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1PTWR, + .name = "smmu1ptwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1CTWR, + .name = "smmu1ctwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR, + .name = "smmu1cmdqvr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW, + .name = "smmu1cmdqvw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW, + .name = "smmu1evntqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2PTWR, + .name = "smmu2ptwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2CTWR, + .name = "smmu2ctwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR, + .name = "smmu2cmdqvr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW, + .name = "smmu2cmdqvw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW, + .name = "smmu2evntqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQR, + .name = "smmu0cmdqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQR, + .name = "smmu1cmdqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQR, + .name = "smmu2cmdqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_APE1R, + .name = "ape1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_APE1W, + .name = "ape1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_UFSR, + .name = "ufsr", + }, { + .id = TEGRA264_MEMORY_CLIENT_UFSW, + .name = "ufsw", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEVR, + .name = "xusb_devr", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEVW, + .name = "xusb_devw", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1R, + .name = "xusb_dev1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2W, + .name = "xusb_dev2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3R, + .name = "xusb_dev3r", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3W, + .name = "xusb_dev3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4R, + .name = "xusb_dev4r", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4W, + .name = "xusb_dev4w", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5R, + .name = "xusb_dev5r", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5W, + .name = "xusb_dev5w", + }, { + .id = TEGRA264_MEMORY_CLIENT_DCER, + .name = "dcer", + }, { + .id = TEGRA264_MEMORY_CLIENT_DCEW, + .name = "dcew", + }, { + .id = TEGRA264_MEMORY_CLIENT_HDAR, + .name = "hdar", + .bpmp_id = TEGRA264_BWMGR_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + }, { + .id = TEGRA264_MEMORY_CLIENT_HDAW, + .name = "hdaw", + .bpmp_id = TEGRA264_BWMGR_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + }, { + .id = TEGRA264_MEMORY_CLIENT_DISPNISOR, + .name = "dispnisor", + }, { + .id = TEGRA264_MEMORY_CLIENT_DISPNISOW, + .name = "dispnisow", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1W, + .name = "xusb_dev1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2R, + .name = "xusb_dev2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_DISPR, + .name = "dispr", + .bpmp_id = TEGRA264_BWMGR_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + }, { + .id = TEGRA264_MEMORY_CLIENT_MSSSEQR, + .name = "mssseqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_MSSSEQW, + .name = "mssseqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3PTWR, + .name = "smmu3ptwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3CTWR, + .name = "smmu3ctwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR, + .name = "smmu3cmdqvr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW, + .name = "smmu3cmdqvw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW, + .name = "smmu3evntqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQR, + .name = "smmu3cmdqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4PTWR, + .name = "smmu4ptwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4CTWR, + .name = "smmu4ctwr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR, + .name = "smmu4cmdqvr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW, + .name = "smmu4cmdqvw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW, + .name = "smmu4evntqw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQR, + .name = "smmu4cmdqr", + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE0R, + .name = "mgbe0r", + .bpmp_id = TEGRA264_BWMGR_EQOS, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE0W, + .name = "mgbe0w", + .bpmp_id = TEGRA264_BWMGR_EQOS, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE1R, + .name = "mgbe1r", + .bpmp_id = TEGRA264_BWMGR_EQOS, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_MGBE1W, + .name = "mgbe1w", + .bpmp_id = TEGRA264_BWMGR_EQOS, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_VI1W, + .name = "vi1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_VIFALCON1R, + .name = "vifalcon1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_VIFALCON1W, + .name = "vifalcon1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISPFALCON1R, + .name = "ispfalcon1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISPFALCON1W, + .name = "ispfalcon1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_RCE1R, + .name = "rce1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_RCE1W, + .name = "rce1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU2R, + .name = "seu2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU2W, + .name = "seu2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU3R, + .name = "seu3r", + }, { + .id = TEGRA264_MEMORY_CLIENT_SEU3W, + .name = "seu3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA0R, + .name = "pva0r", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA0W, + .name = "pva0w", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA1R, + .name = "pva1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA1W, + .name = "pva1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA2R, + .name = "pva2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_PVA2W, + .name = "pva2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISP3W, + .name = "isp3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISP2R, + .name = "isp2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_ISP2W, + .name = "isp2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_EQOSR, + .name = "eqosr", + }, { + .id = TEGRA264_MEMORY_CLIENT_EQOSW, + .name = "eqosw", + }, { + .id = TEGRA264_MEMORY_CLIENT_FSI0R, + .name = "fsi0r", + }, { + .id = TEGRA264_MEMORY_CLIENT_FSI0W, + .name = "fsi0w", + }, { + .id = TEGRA264_MEMORY_CLIENT_FSI1R, + .name = "fsi1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_FSI1W, + .name = "fsi1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_SDMMC0R, + .name = "sdmmc0r", + .bpmp_id = TEGRA264_BWMGR_SDMMC_1, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_SDMMC0W, + .name = "sdmmc0w", + .bpmp_id = TEGRA264_BWMGR_SDMMC_1, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA264_MEMORY_CLIENT_SBR, + .name = "sbr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SBW, + .name = "sbw", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU0R, + .name = "hss_miu0r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU0W, + .name = "hss_miu0w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU1R, + .name = "hss_miu1r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU1W, + .name = "hss_miu1w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU2R, + .name = "hss_miu2r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU2W, + .name = "hss_miu2w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU3R, + .name = "hss_miu3r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU3W, + .name = "hss_miu3w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU4R, + .name = "hss_miu4r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU4W, + .name = "hss_miu4w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU5R, + .name = "hss_miu5r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU5W, + .name = "hss_miu5w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU6R, + .name = "hss_miu6r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU6W, + .name = "hss_miu6w", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU7R, + .name = "hss_miu7r", + }, { + .id = TEGRA264_MEMORY_CLIENT_HSS_MIU7W, + .name = "hss_miu7w", + }, { + .id = TEGRA264_MEMORY_CLIENT_GMMUR2MC, + .name = "gmmur2mc", + }, { + .id = TEGRA264_MEMORY_CLIENT_UCFELAR, + .name = "ucfelar", + }, { + .id = TEGRA264_MEMORY_CLIENT_UCFELAW, + .name = "ucfelaw", + }, { + .id = TEGRA264_MEMORY_CLIENT_SLCR, + .name = "slcr", + }, { + .id = TEGRA264_MEMORY_CLIENT_SLCW, + .name = "slcw", + }, { + .id = TEGRA264_MEMORY_CLIENT_REMOTER, + .name = "remoter", + }, { + .id = TEGRA264_MEMORY_CLIENT_REMOTEW, + .name = "remotew", }, }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] memory: tegra264: Add full set of MC clients 2026-05-18 12:43 ` [PATCH v2 3/3] memory: tegra264: Add full set of MC clients Sumit Gupta @ 2026-05-18 13:33 ` sashiko-bot 2026-05-18 18:01 ` Sumit Gupta 0 siblings, 1 reply; 8+ messages in thread From: sashiko-bot @ 2026-05-18 13:33 UTC (permalink / raw) To: Sumit Gupta; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] Newly added BPMP-managed memory clients are missing their `.bpmp_id` and `.type` interconnect properties. -- commit 1230942ec14ede13ea86a9f95a6ff94371903b6d Author: Sumit Gupta <sumitg@nvidia.com> memory: tegra264: Add full set of MC clients This commit extends the tegra264_mc_clients table to include the full set of memory clients exposed by the SoC. The commit message notes that clients managed by the BPMP bandwidth manager additionally carry their bpmp_id and type. > diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra264.c > index e628908417255..b8d6c4ce48369 100644 > --- a/drivers/memory/tegra/tegra264.c > +++ b/drivers/memory/tegra/tegra264.c [ ... ] > @@ -21,45 +21,62 @@ > */ > static const struct tegra_mc_client tegra264_mc_clients[] = { [ ... ] > + }, { > + .id = TEGRA264_MEMORY_CLIENT_MGBE2R, > + .name = "mgbe2r", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_OFAR2MC, > + .name = "ofar2mc", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_OFAW2MC, > + .name = "ofaw2mc", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_MGBE2W, > + .name = "mgbe2w", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_MGBE3R, > + .name = "mgbe3r", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_MGBE3W, > + .name = "mgbe3w", Are the new MGBE2 and MGBE3 clients missing their interconnect properties? Looking at the other EQOS clients like MGBE0R and MGBE1R, they correctly initialize .bpmp_id = TEGRA264_BWMGR_EQOS and .type = TEGRA_ICC_NISO. If these fields are omitted for MGBE2 and MGBE3, won't interconnect bandwidth scaling requests for these blocks be silently ignored, potentially causing hardware bandwidth starvation? [ ... ] > @@ -70,6 +87,15 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { > .name = "vicw", > .bpmp_id = TEGRA264_BWMGR_VIC, > .type = TEGRA_ICC_NISO, > + }, { > + .id = TEGRA264_MEMORY_CLIENT_VIW, > + .name = "viw", Does this missing bpmp_id issue also apply to other BPMP-managed subsystems added in this patch, such as VIW? [ ... ] > @@ -110,6 +208,12 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { > .name = "rcew", > .bpmp_id = TEGRA264_BWMGR_RCE, > .type = TEGRA_ICC_NISO, > + }, { > + .id = TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC, > + .name = "nvenc1srd2mc", > + }, { > + .id = TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC, > + .name = "nvenc1swr2mc", Are these newly added NVENC clients also missing their TEGRA264_BWMGR_NVENC manager definitions? Since the memory controller interconnect implementation skips bandwidth scaling requests for clients without a bpmp_id, should these clients also include their respective bpmp_id and type to ensure bandwidth requests are processed? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260518124306.2071481-1-sumitg@nvidia.com?part=3 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] memory: tegra264: Add full set of MC clients 2026-05-18 13:33 ` sashiko-bot @ 2026-05-18 18:01 ` Sumit Gupta 0 siblings, 0 replies; 8+ messages in thread From: Sumit Gupta @ 2026-05-18 18:01 UTC (permalink / raw) To: sashiko-reviews; +Cc: conor+dt, devicetree, robh, sumitg On 18/05/26 19:03, sashiko-bot@kernel.org wrote: > External email: Use caution opening links or attachments > > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [High] Newly added BPMP-managed memory clients are missing their `.bpmp_id` and `.type` interconnect properties. > -- In v2, added new 'patch 1/3' which adds a check to skip ICC requests for clients without .bpmp_id/.type, so they are not sent to BPMP. Thank you, Sumit Gupta > > commit 1230942ec14ede13ea86a9f95a6ff94371903b6d > Author: Sumit Gupta <sumitg@nvidia.com> > > memory: tegra264: Add full set of MC clients > > This commit extends the tegra264_mc_clients table to include the full set of > memory clients exposed by the SoC. The commit message notes that clients > managed by the BPMP bandwidth manager additionally carry their bpmp_id and > type. > >> diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra264.c >> index e628908417255..b8d6c4ce48369 100644 >> --- a/drivers/memory/tegra/tegra264.c >> +++ b/drivers/memory/tegra/tegra264.c > [ ... ] >> @@ -21,45 +21,62 @@ >> */ >> static const struct tegra_mc_client tegra264_mc_clients[] = { > [ ... ] >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_MGBE2R, >> + .name = "mgbe2r", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_OFAR2MC, >> + .name = "ofar2mc", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_OFAW2MC, >> + .name = "ofaw2mc", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_MGBE2W, >> + .name = "mgbe2w", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_MGBE3R, >> + .name = "mgbe3r", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_MGBE3W, >> + .name = "mgbe3w", > Are the new MGBE2 and MGBE3 clients missing their interconnect properties? > > Looking at the other EQOS clients like MGBE0R and MGBE1R, they correctly > initialize .bpmp_id = TEGRA264_BWMGR_EQOS and .type = TEGRA_ICC_NISO. If > these fields are omitted for MGBE2 and MGBE3, won't interconnect bandwidth > scaling requests for these blocks be silently ignored, potentially causing > hardware bandwidth starvation? > > [ ... ] >> @@ -70,6 +87,15 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { >> .name = "vicw", >> .bpmp_id = TEGRA264_BWMGR_VIC, >> .type = TEGRA_ICC_NISO, >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_VIW, >> + .name = "viw", > Does this missing bpmp_id issue also apply to other BPMP-managed > subsystems added in this patch, such as VIW? > > [ ... ] >> @@ -110,6 +208,12 @@ static const struct tegra_mc_client tegra264_mc_clients[] = { >> .name = "rcew", >> .bpmp_id = TEGRA264_BWMGR_RCE, >> .type = TEGRA_ICC_NISO, >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC, >> + .name = "nvenc1srd2mc", >> + }, { >> + .id = TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC, >> + .name = "nvenc1swr2mc", > Are these newly added NVENC clients also missing their TEGRA264_BWMGR_NVENC > manager definitions? > > Since the memory controller interconnect implementation skips bandwidth > scaling requests for clients without a bpmp_id, should these clients also > include their respective bpmp_id and type to ensure bandwidth requests > are processed? > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260518124306.2071481-1-sumitg@nvidia.com?part=3 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-05-18 18:01 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-18 12:43 [PATCH v2 0/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 1/3] memory: tegra264: Skip clients without bpmp_id or type Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 2/3] dt-bindings: memory: tegra264: Add full set of MC client IDs Sumit Gupta 2026-05-18 13:10 ` sashiko-bot 2026-05-18 17:51 ` Sumit Gupta 2026-05-18 12:43 ` [PATCH v2 3/3] memory: tegra264: Add full set of MC clients Sumit Gupta 2026-05-18 13:33 ` sashiko-bot 2026-05-18 18:01 ` Sumit Gupta
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