From: sashiko-bot@kernel.org
To: "Sibi Sankar" <sibi.sankar@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH V8 1/2] arm64: dts: glymur: Add LPASS macro codecs and pinctrl
Date: Wed, 20 May 2026 14:44:32 +0000 [thread overview]
Message-ID: <20260520144434.006F21F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260520141828.2724689-2-sibi.sankar@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The SoundWire nodes ('swr0' and 'swr3') define 17 elements for 'qcom,ports-*' arrays, which violates the DT binding schema.
--
commit 46878976f64d7da2480d0d9a2b1541da162ac28d
Author: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
arm64: dts: glymur: Add LPASS macro codecs and pinctrl
Add LPASS macro codecs, LPASS TLMM pin controller, and GPR node along with
APM and PRM audio services on Qualcomm glymur for proper sound support.
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 72c7dc6e4f098..f89b9c3b54521 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[ ... ]
> + swr0: soundwire@6c80000 {
> + compatible = "qcom,soundwire-v3.1.0";
> + reg = <0x0 0x06c80000 0x0 0x10000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&lpass_wsamacro>;
> + clock-names = "iface";
> + label = "WSA";
> +
> + pinctrl-0 = <&wsa_swr_active>;
> + pinctrl-names = "default";
> +
> + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>;
> + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>;
> + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>;
> + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
> + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >;
> + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>;
> + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>;
> + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
[Severity: Low]
Is it possible that these arrays define too many elements for the binding
schema?
The DT binding schema for qcom,soundwire enforces a maximum of 16 items for
properties like qcom,ports-block-pack-mode and qcom,ports-word-length. It
appears these arrays define 17 elements, which might cause DT validation to
fail during dtbs_check.
[ ... ]
> + swr3: soundwire@6ca0000 {
> + compatible = "qcom,soundwire-v3.1.0";
> + reg = <0x0 0x06ca0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&lpass_wsa2macro>;
> + clock-names = "iface";
> + label = "WSA2";
> +
> + pinctrl-0 = <&wsa2_swr_active>;
> + pinctrl-names = "default";
> +
> + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>;
> + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>;
> + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>;
> + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
> + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >;
> + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>;
> + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>;
> + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
[Severity: Low]
Could this node also trigger the same validation issue?
These arrays similarly define 17 elements.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260520141828.2724689-1-sibi.sankar@oss.qualcomm.com?part=1
next prev parent reply other threads:[~2026-05-20 14:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 14:18 [PATCH V8 0/2] Enable ADSP and CDSP for Glymur SoC Sibi Sankar
2026-05-20 14:18 ` [PATCH V8 1/2] arm64: dts: glymur: Add LPASS macro codecs and pinctrl Sibi Sankar
2026-05-20 14:44 ` sashiko-bot [this message]
2026-05-20 14:18 ` [PATCH V8 2/2] arm64: dts: qcom: glymur-crd: add Audio sound card node Sibi Sankar
2026-05-20 15:06 ` sashiko-bot
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