* [PATCH v3 0/1] add PWM DTS support for S32G2/S32G3 SoCs
@ 2026-05-29 7:05 Khristine Andreea Barbulescu
2026-05-29 7:05 ` [PATCH v3 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3 Khristine Andreea Barbulescu
0 siblings, 1 reply; 3+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-29 7:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
This patchset aims to add one change to the S32G2/S32G3 dtsi support:
- Add PWM dts support for S32G SoC based boards
v3 -> v2:
- remove vendor internal issue tracker
v2 -> v1:
- fix indentation alignment
- use hyphens for pwm pinctrl nodes
- sort pwm nodes alphabetically
Khristine Andreea Barbulescu (1):
arm64: dts: s32g: add PWM support for s32g2 and s32g3
arch/arm64/boot/dts/freescale/s32g2.dtsi | 28 ++++++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 30 ++++++-
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 78 ++++++++++++++++++-
3 files changed, 133 insertions(+), 3 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3
2026-05-29 7:05 [PATCH v3 0/1] add PWM DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu
@ 2026-05-29 7:05 ` Khristine Andreea Barbulescu
2026-05-29 7:24 ` sashiko-bot
0 siblings, 1 reply; 3+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-29 7:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
Add PWM0 and PWM1 for S32G2 and S32G3 SoCs
Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 28 ++++++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 30 ++++++-
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 78 ++++++++++++++++++-
3 files changed, 133 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..9f5f18d54118 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -554,6 +554,19 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
+ pwm0: pwm@401f4000 {
+ compatible = "nxp,s32g2-ftm-pwm";
+ reg = <0x401f4000 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clks 5>,
+ <&clks 6>,
+ <&clks 5>,
+ <&clks 5>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -717,6 +730,19 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
+ pwm1: pwm@402e4000 {
+ compatible = "nxp,s32g2-ftm-pwm";
+ reg = <0x402e4000 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clks 7>,
+ <&clks 8>,
+ <&clks 7>,
+ <&clks 7>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..408bf0b40734 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -617,6 +617,20 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
+ pwm0: pwm@401f4000 {
+ compatible = "nxp,s32g3-ftm-pwm",
+ "nxp,s32g2-ftm-pwm";
+ reg = <0x401f4000 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clks 5>,
+ <&clks 6>,
+ <&clks 5>,
+ <&clks 5>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -792,6 +806,20 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
+ pwm1: pwm@402e4000 {
+ compatible = "nxp,s32g3-ftm-pwm",
+ "nxp,s32g2-ftm-pwm";
+ reg = <0x402e4000 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clks 7>,
+ <&clks 8>,
+ <&clks 7>,
+ <&clks 7>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index 803ff4531077..844d2c4fabf7 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
*
* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
@@ -245,6 +245,70 @@ dspi5-grp4 {
bias-pull-up;
};
};
+
+ ftm0_pins: ftm0_pins {
+ ftm0_grp0 {
+ pinmux = <0x2912>;
+ };
+
+ ftm0_grp1 {
+ pinmux = <0x122>,
+ <0xb42>;
+ output-enable;
+ input-enable;
+ };
+
+ ftm0_grp2 {
+ pinmux = <0xb13>,
+ <0xb53>;
+ output-enable;
+ input-enable;
+ };
+
+ ftm0_grp3 {
+ pinmux = <0x2904>;
+ };
+
+ ftm0_grp4 {
+ pinmux = <0x2925>;
+ };
+
+ ftm0_grp5 {
+ pinmux = <0x2936>;
+ };
+ };
+
+ ftm1_pins: ftm1_pins {
+ ftm1_grp0 {
+ pinmux = <0x1d3>;
+ output-enable;
+ input-enable;
+ };
+
+ ftm1_grp1 {
+ pinmux = <0x29b4>;
+ };
+
+ ftm1_grp2 {
+ pinmux = <0x29c3>;
+ };
+
+ ftm1_grp3 {
+ pinmux = <0x1f4>;
+ output-enable;
+ input-enable;
+ };
+
+ ftm1_grp4 {
+ pinmux = <0x202>;
+ output-enable;
+ input-enable;
+ };
+
+ ftm1_grp5 {
+ pinmux = <0x29d2>;
+ };
+ };
};
&can0 {
@@ -304,3 +368,15 @@ &spi5 {
pinctrl-names = "default";
status = "okay";
};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ftm0_pins>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ftm1_pins>;
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3
2026-05-29 7:05 ` [PATCH v3 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3 Khristine Andreea Barbulescu
@ 2026-05-29 7:24 ` sashiko-bot
0 siblings, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-05-29 7:24 UTC (permalink / raw)
To: Khristine Andreea Barbulescu; +Cc: robh, conor+dt, imx, Frank.Li, devicetree
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Devicetree node names use underscores instead of hyphens.
- [Low] Inconsistent indentation for property continuations in DTS nodes.
--
commit ffbe8dd9e7b30291bb99de8bc8fc2e7bc1d421ea
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
arm64: dts: s32g: add PWM support for s32g2 and s32g3
This commit adds PWM0 and PWM1 nodes for S32G2 and S32G3 SoCs. It configures
the device nodes in the respective dtsi files and adds the corresponding
pinctrl configurations in the EVB dtsi.
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12deb..9f5f18d541183 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[ ... ]
> @@ -554,6 +554,19 @@ i2c2: i2c@401ec000 {
> status = "disabled";
> };
>
> + pwm0: pwm@401f4000 {
> + compatible = "nxp,s32g2-ftm-pwm";
> + reg = <0x401f4000 0x1000>;
> + #pwm-cells = <3>;
> + clocks = <&clks 5>,
> + <&clks 6>,
> + <&clks 5>,
> + <&clks 5>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
[Severity: Low]
This isn't a bug, but there is an indentation inconsistency here. The second
line of the clock-names property appears to be over-indented compared to the
alignment used in the pwm1 node. Should this align evenly with the strings on
the first line?
> + status = "disabled";
> + };
> +
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d0..408bf0b407346 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
[ ... ]
> @@ -617,6 +617,20 @@ i2c2: i2c@401ec000 {
> status = "disabled";
> };
>
> + pwm0: pwm@401f4000 {
> + compatible = "nxp,s32g3-ftm-pwm",
> + "nxp,s32g2-ftm-pwm";
[Severity: Low]
This isn't a bug, but similarly to the clock-names above, the compatible
string continuation appears to be over-indented. Would it be better to align
it evenly with the first string?
> + reg = <0x401f4000 0x1000>;
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index 803ff45310771..844d2c4fabf76 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
[ ... ]
> @@ -245,6 +245,70 @@ dspi5-grp4 {
> bias-pull-up;
> };
> };
> +
> + ftm0_pins: ftm0_pins {
> + ftm0_grp0 {
> + pinmux = <0x2912>;
> + };
[Severity: Low]
This isn't a bug, but the Devicetree specification generally recommends using
hyphens instead of underscores for node names to avoid dtc warnings. Should
these node names be changed to use hyphens (e.g., ftm0-pins and ftm0-grp0) to
stay consistent with other nodes like dspi5-grp4 in this file? The node
labels (ftm0_pins:) can safely keep their underscores.
> +
> + ftm0_grp1 {
> + pinmux = <0x122>,
> + <0xb42>;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260529070502.1749632-2-khristineandreea.barbulescu@oss.nxp.com?part=1
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2026-05-29 7:05 [PATCH v3 0/1] add PWM DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu
2026-05-29 7:05 ` [PATCH v3 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3 Khristine Andreea Barbulescu
2026-05-29 7:24 ` sashiko-bot
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