[PATCH v2 0/2] Add support for Renesas RZ/G3L LVDS encoder

[PATCH v2 0/2] Add support for Renesas RZ/G3L LVDS encoder

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for the RZ/G3L LVDS encoder driver. It operates in single-link
mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates
from 25 to 87 MHz. The LVDS module cannot be used at the same time as
MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and
MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS
module.

v2->v3:
 * Dropped patch#1 as it is accepted.
 * Replace drm_atomic_state with drm_atomic_commit in
   rzg3l_lvds_atomic_{en,dis}able().
 * Drop local variable ret and dev_err() messages in
   rzg3l_lvds_atomic_enable(); use WARN_ON() instead to
   capture unexpected failures since atomic_enable should not fail.
 * Drop local variable next_bridge from rzg3l_lvds_probe().
v1->v2:
 * Collected the tags for binding patches.
 * Dropped unused function rzg3l_lvds_is_connected() and removed the 
   corresponding header file rzg3l_lvds.h
 * Dropped next_bridge from struct rzg3l_lvds instead using bridge's
   next_bridge.
 * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as
   atomic_enable doesn't fail and for each enable there always will be an
   atomic_disable() call.
 * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback.
 * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in probe()
 * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend,
   resume}().

Biju Das (2):
  dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
  drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder

 .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++
 drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
 drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 277 ++++++++++++++++++
 .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  26 ++
 5 files changed, 445 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h

-- 
2.43.0

[PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode. LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be
used at the same time as MIPI-DSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Collected tag.
---
 .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
new file mode 100644
index 000000000000..b1f6d020ae7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3L LVDS Encoder
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
+
+description: |
+  This binding describe the LVDS encoder embedded in the Renesas RZ/G3L
+  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
+  (Data) + 1 lane (Clock).
+
+properties:
+  compatible:
+    const: renesas,r9a08g046-lvds
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Peripheral clock
+      - description: PHY clock
+      - description: Dot clock
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: phyclk
+      - const: dotclk
+
+  resets:
+    items:
+      - description: LVDS_RESET_N
+      - description: MIPI_DSI_PRESET_N
+      - description: MIPI_DSI_CMN_RSTB
+      - description: MIPI_DSI_ARESET_N
+
+  reset-names:
+    items:
+      - const: lvdrst
+      - const: prst
+      - const: rst
+      - const: arst
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input channel, directly connected to the Display Unit.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          Output channel, directly connected to the LVDS panel or bridge.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
+
+    lvds-cmn@108a0000 {
+        compatible = "renesas,r9a08g046-lvds-cmn",
+                     "simple-mfd", "syscon";
+        reg = <0x108a0000 0x10000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        lvds0: lvds@10 {
+            compatible = "renesas,r9a08g046-lvds";
+            reg = <0x10 0x8>;
+            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
+                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
+                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
+            clock-names = "pclk", "phyclk", "dotclk";
+            resets = <&cpg R9A08G046_LVDS_RESET_N>,
+                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
+                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
+                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
+            reset-names = "lvdrst", "prst", "rst", "arst";
+            power-domains = <&cpg>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    lvds0_in: endpoint {
+                        remote-endpoint = <&du_out_lvds0>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    lvds0_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                    };
+                };
+            };
+        };
+    };
+...
-- 
2.43.0

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
- [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
--

commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
Author: Biju Das <biju.das.jz@bp.renesas.com>

dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode and shares a peripheral clock and reset signal with the
MIPI-DSI interface.

> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> new file mode 100644
> index 0000000000000..b1f6d020ae7b1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> +    lvds-cmn@108a0000 {
> +        compatible = "renesas,r9a08g046-lvds-cmn",
> +                     "simple-mfd", "syscon";

[Severity: Low]
Is this compatible string documented somewhere else? It looks like
renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
dt_binding_check to fail when it validates the example.

> +        reg = <0x108a0000 0x10000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;

[Severity: Low]
Does this parent node need a ranges property? Without it, address translation
for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
missing ranges in simple-mfd nodes with children.

> +
> +        lvds0: lvds@10 {
> +            compatible = "renesas,r9a08g046-lvds";
> +            reg = <0x10 0x8>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260524194457.479681-1-biju.das.jz@bp.renesas.com?part=1

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

Hi Bot,

On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
>
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> --
>
> commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> Author: Biju Das <biju.das.jz@bp.renesas.com>
>
> dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
>
> Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> single-link mode and shares a peripheral clock and reset signal with the
> MIPI-DSI interface.
>
> > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > new file mode 100644
> > index 0000000000000..b1f6d020ae7b1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
>
> [ ... ]
>
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > +
> > +    lvds-cmn@108a0000 {
> > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > +                     "simple-mfd", "syscon";
>
> [Severity: Low]
> Is this compatible string documented somewhere else? It looks like
> renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> dt_binding_check to fail when it validates the example.

This compatible is documented and is in next [1].

Q1) Can you please reun the AI review with [1] ?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88

>
> > +        reg = <0x108a0000 0x10000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
>
> [Severity: Low]
> Does this parent node need a ranges property? Without it, address translation
> for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> missing ranges in simple-mfd nodes with children.

I don't get any error or dtc warnings. Have you ran dt-binding check
before providing
such comment?

Cheers,
Biju

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2574 bytes --]

On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> Hi Bot,
> 
> On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> >
> > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> > --
> >
> > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > Author: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> >
> > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode and shares a peripheral clock and reset signal with the
> > MIPI-DSI interface.
> >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > > new file mode 100644
> > > index 0000000000000..b1f6d020ae7b1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> >
> > [ ... ]
> >
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > +
> > > +    lvds-cmn@108a0000 {
> > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > +                     "simple-mfd", "syscon";
> >
> > [Severity: Low]
> > Is this compatible string documented somewhere else? It looks like
> > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> > dt_binding_check to fail when it validates the example.
> 
> This compatible is documented and is in next [1].
> 
> Q1) Can you please reun the AI review with [1] ?
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> 
> >
> > > +        reg = <0x108a0000 0x10000>;
> > > +        #address-cells = <1>;
> > > +        #size-cells = <1>;
> >
> > [Severity: Low]
> > Does this parent node need a ranges property? Without it, address translation
> > for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> > missing ranges in simple-mfd nodes with children.
> 
> I don't get any error or dtc warnings. Have you ran dt-binding check
> before providing
> such comment?

From what I can establish, it mentions the checks etc but never actually
runs them.

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Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Sun, May 24, 2026 at 08:44:50PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
> single-link mode. LVDS and the DSI interface share a peripheral clock and
> the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be
> used at the same time as MIPI-DSI.
> 

Same here, this should be v3 instead of v2.
Apart from that patch LGTM.

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind Regards,
Tommaso

> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Collected tag.
> ---
>  .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
>  1 file changed, 128 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> new file mode 100644
> index 000000000000..b1f6d020ae7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> @@ -0,0 +1,128 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3L LVDS Encoder
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> +
> +description: |
> +  This binding describe the LVDS encoder embedded in the Renesas RZ/G3L
> +  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
> +  (Data) + 1 lane (Clock).
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a08g046-lvds
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Peripheral clock
> +      - description: PHY clock
> +      - description: Dot clock
> +
> +  clock-names:
> +    items:
> +      - const: pclk
> +      - const: phyclk
> +      - const: dotclk
> +
> +  resets:
> +    items:
> +      - description: LVDS_RESET_N
> +      - description: MIPI_DSI_PRESET_N
> +      - description: MIPI_DSI_CMN_RSTB
> +      - description: MIPI_DSI_ARESET_N
> +
> +  reset-names:
> +    items:
> +      - const: lvdrst
> +      - const: prst
> +      - const: rst
> +      - const: arst
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: Input channel, directly connected to the Display Unit.
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: |
> +          Output channel, directly connected to the LVDS panel or bridge.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> +    lvds-cmn@108a0000 {
> +        compatible = "renesas,r9a08g046-lvds-cmn",
> +                     "simple-mfd", "syscon";
> +        reg = <0x108a0000 0x10000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        lvds0: lvds@10 {
> +            compatible = "renesas,r9a08g046-lvds";
> +            reg = <0x10 0x8>;
> +            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> +                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> +            clock-names = "pclk", "phyclk", "dotclk";
> +            resets = <&cpg R9A08G046_LVDS_RESET_N>,
> +                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> +                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> +            reset-names = "lvdrst", "prst", "rst", "arst";
> +            power-domains = <&cpg>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port@0 {
> +                    reg = <0>;
> +                    lvds0_in: endpoint {
> +                        remote-endpoint = <&du_out_lvds0>;
> +                    };
> +                };
> +
> +                port@1 {
> +                    reg = <1>;
> +                    lvds0_out: endpoint {
> +                        remote-endpoint = <&panel_in>;
> +                    };
> +                };
> +            };
> +        };
> +    };
> +...
> -- 
> 2.43.0
> 

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

Hi Tommaso,

Thanks for the feedback.

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Sent: 26 May 2026 08:07
> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> 
> Hi Biju,
> Thanks for your patch.
> 
> On Sun, May 24, 2026 at 08:44:50PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode. LVDS and the DSI interface share a peripheral clock
> > and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module
> > cannot be used at the same time as MIPI-DSI.
> >
> 
> Same here, this should be v3 instead of v2.

Will send this as v3.

Cheers,
Biju

> Apart from that patch LGTM.
> 
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> Kind Regards,
> Tommaso
> 
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * No change.
> > v1->v2:
> >  * Collected tag.
> > ---
> >  .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
> >  1 file changed, 128 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvd
> > s.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l
> > vds.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l
> > vds.yaml
> > new file mode 100644
> > index 000000000000..b1f6d020ae7b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g0
> > +++ 46-lvds.yaml
> > @@ -0,0 +1,128 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.y
> > +aml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/G3L LVDS Encoder
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > +
> > +description: |
> > +  This binding describe the LVDS encoder embedded in the Renesas
> > +RZ/G3L
> > +  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
> > +  (Data) + 1 lane (Clock).
> > +
> > +properties:
> > +  compatible:
> > +    const: renesas,r9a08g046-lvds
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Peripheral clock
> > +      - description: PHY clock
> > +      - description: Dot clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pclk
> > +      - const: phyclk
> > +      - const: dotclk
> > +
> > +  resets:
> > +    items:
> > +      - description: LVDS_RESET_N
> > +      - description: MIPI_DSI_PRESET_N
> > +      - description: MIPI_DSI_CMN_RSTB
> > +      - description: MIPI_DSI_ARESET_N
> > +
> > +  reset-names:
> > +    items:
> > +      - const: lvdrst
> > +      - const: prst
> > +      - const: rst
> > +      - const: arst
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +
> > +    properties:
> > +      port@0:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: Input channel, directly connected to the Display Unit.
> > +
> > +      port@1:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: |
> > +          Output channel, directly connected to the LVDS panel or bridge.
> > +
> > +    required:
> > +      - port@0
> > +      - port@1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - resets
> > +  - reset-names
> > +  - power-domains
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > +
> > +    lvds-cmn@108a0000 {
> > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > +                     "simple-mfd", "syscon";
> > +        reg = <0x108a0000 0x10000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +
> > +        lvds0: lvds@10 {
> > +            compatible = "renesas,r9a08g046-lvds";
> > +            reg = <0x10 0x8>;
> > +            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> > +                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> > +                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> > +            clock-names = "pclk", "phyclk", "dotclk";
> > +            resets = <&cpg R9A08G046_LVDS_RESET_N>,
> > +                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> > +                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> > +                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> > +            reset-names = "lvdrst", "prst", "rst", "arst";
> > +            power-domains = <&cpg>;
> > +
> > +            ports {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +
> > +                port@0 {
> > +                    reg = <0>;
> > +                    lvds0_in: endpoint {
> > +                        remote-endpoint = <&du_out_lvds0>;
> > +                    };
> > +                };
> > +
> > +                port@1 {
> > +                    reg = <1>;
> > +                    lvds0_out: endpoint {
> > +                        remote-endpoint = <&panel_in>;
> > +                    };
> > +                };
> > +            };
> > +        };
> > +    };
> > +...
> > --
> > 2.43.0
> >

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Rob Herring]

On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> Hi Bot,
> 
> On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> >
> > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> > --
> >
> > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > Author: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> >
> > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode and shares a peripheral clock and reset signal with the
> > MIPI-DSI interface.
> >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > > new file mode 100644
> > > index 0000000000000..b1f6d020ae7b1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> >
> > [ ... ]
> >
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > +
> > > +    lvds-cmn@108a0000 {
> > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > +                     "simple-mfd", "syscon";
> >
> > [Severity: Low]
> > Is this compatible string documented somewhere else? It looks like
> > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> > dt_binding_check to fail when it validates the example.
> 
> This compatible is documented and is in next [1].
> 
> Q1) Can you please reun the AI review with [1] ?
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> 
> >
> > > +        reg = <0x108a0000 0x10000>;
> > > +        #address-cells = <1>;
> > > +        #size-cells = <1>;
> >
> > [Severity: Low]
> > Does this parent node need a ranges property? Without it, address translation
> > for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> > missing ranges in simple-mfd nodes with children.
> 
> I don't get any error or dtc warnings. Have you ran dt-binding check
> before providing
> such comment?

There probably isn't any warning, but sashiko is correct that 'ranges' 
should be present. The schema for the parent should require 'ranges'. 
The 'simple-mfd' binding does not as not all simple-mfd's have MMIO 
addresess in the child nodes.

Rob