* [PATCH] arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI
@ 2026-06-01 11:38 Marek Vasut
2026-06-01 11:45 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2026-06-01 11:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Magnus Damm, Rob Herring, devicetree,
linux-kernel, linux-renesas-soc
Add PSCI "enable-method" DT property to all application CPU cores.
This allows the OS to bring application CPU cores up and down.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
NOTE: This depends mainline TFA 2.15 or newer (or SDK TFA version
which includes b950bc09f5e9 ("plat: rcar_gen5: Fix multicore
boot by ensuring fixed address for plat_secondary_reset"))
and on SDK 4.32 or newer SCP firmware.
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 7780fb4e8351d..fb71974ef3905 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -143,6 +143,7 @@ a720_0: cpu@0 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x0>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_0>;
};
@@ -150,6 +151,7 @@ a720_1: cpu@100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_1>;
};
@@ -157,6 +159,7 @@ a720_2: cpu@200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_2>;
};
@@ -164,6 +167,7 @@ a720_3: cpu@300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_3>;
};
@@ -171,6 +175,7 @@ a720_4: cpu@10000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_4>;
};
@@ -178,6 +183,7 @@ a720_5: cpu@10100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_5>;
};
@@ -185,6 +191,7 @@ a720_6: cpu@10200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_6>;
};
@@ -192,6 +199,7 @@ a720_7: cpu@10300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_7>;
};
@@ -199,6 +207,7 @@ a720_8: cpu@20000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_8>;
};
@@ -206,6 +215,7 @@ a720_9: cpu@20100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_9>;
};
@@ -213,6 +223,7 @@ a720_10: cpu@20200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_10>;
};
@@ -220,6 +231,7 @@ a720_11: cpu@20300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_11>;
};
@@ -227,6 +239,7 @@ a720_12: cpu@30000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_12>;
};
@@ -234,6 +247,7 @@ a720_13: cpu@30100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_13>;
};
@@ -241,6 +255,7 @@ a720_14: cpu@30200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_14>;
};
@@ -248,6 +263,7 @@ a720_15: cpu@30300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_15>;
};
@@ -255,6 +271,7 @@ a720_16: cpu@40000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_16>;
};
@@ -262,6 +279,7 @@ a720_17: cpu@40100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_17>;
};
@@ -269,6 +287,7 @@ a720_18: cpu@40200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_18>;
};
@@ -276,6 +295,7 @@ a720_19: cpu@40300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_19>;
};
@@ -283,6 +303,7 @@ a720_20: cpu@50000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_20>;
};
@@ -290,6 +311,7 @@ a720_21: cpu@50100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_21>;
};
@@ -297,6 +319,7 @@ a720_22: cpu@50200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_22>;
};
@@ -304,6 +327,7 @@ a720_23: cpu@50300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_23>;
};
@@ -311,6 +335,7 @@ a720_24: cpu@60000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_24>;
};
@@ -318,6 +343,7 @@ a720_25: cpu@60100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_25>;
};
@@ -325,6 +351,7 @@ a720_26: cpu@60200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_26>;
};
@@ -332,6 +359,7 @@ a720_27: cpu@60300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_27>;
};
@@ -339,6 +367,7 @@ a720_28: cpu@70000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70000>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_28>;
};
@@ -346,6 +375,7 @@ a720_29: cpu@70100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70100>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_29>;
};
@@ -353,6 +383,7 @@ a720_30: cpu@70200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70200>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_30>;
};
@@ -360,6 +391,7 @@ a720_31: cpu@70300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70300>;
device_type = "cpu";
+ enable-method = "psci";
next-level-cache = <&L2_CA720_31>;
};
--
2.53.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI
2026-06-01 11:38 [PATCH] arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI Marek Vasut
@ 2026-06-01 11:45 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-06-01 11:45 UTC (permalink / raw)
To: Marek Vasut; +Cc: wsa+renesas, robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `/psci` firmware node prevents PSCI initialization and secondary CPU bring-up.
--
commit 48b96f528db39732a93e926dab244c4a13787175
Author: Marek Vasut <marek.vasut+renesas@mailbox.org>
arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI
This commit adds the PSCI enable-method property to all 32 application CPU
cores in the r8a78000 device tree. This is intended to allow the OS to manage
the secondary CPUs using PSCI firmware.
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 3e1c98903cea0..1ed98545990f2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -143,6 +143,7 @@ a720_0: cpu@0 {
> compatible = "arm,cortex-a720ae";
> reg = <0x0 0x0>;
> device_type = "cpu";
> + enable-method = "psci";
[Severity: High]
Does this device tree lack the required /psci firmware node?
Looking at the new enable-method properties, the CPUs are configured to use
PSCI, but there doesn't appear to be a corresponding psci node in the root
of the device tree.
During early boot, psci_dt_init() in drivers/firmware/psci/psci.c searches
for a node compatible with arm,psci or arm,psci-1.0. If the node is entirely
absent, psci_dt_init() returns -ENODEV and PSCI operations are not registered.
Will this omission cause SMP initialization to fail, leaving the system
forced to run only on the primary boot CPU?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260601113919.8327-1-marek.vasut+renesas@mailbox.org?part=1
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