Re: [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Zic64b validation incorrectly requires all CBO extensions to be present, erroneously disabling Zic64b if any optional CBO extension is unimplemented.
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commit fecaace37b018a89cd6931b57477f69defdbcd61
Author: Guodong Xu <docular.xu@gmail.com>

riscv: Add Zic64b to cpufeature and hwprobe

This commit adds support for the Zic64b extension, which mandates 64-byte
naturally aligned cache blocks. It allocates an ISA extension ID, adds a
validation callback, and exports the feature via hwprobe.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index e0197160af6dd..79ff431768139 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c

[ ... ]

> @@ -154,6 +154,23 @@ static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data,
>  	return 0;
>  }
>  
> +static int riscv_ext_zic64b_validate(const struct riscv_isa_ext_data *data,
> +				     const unsigned long *isa_bitmap)
> +{
> +	/*
> +	 * Zic64b mandates 64-byte naturally aligned cache blocks; cross-check the
> +	 * cbom/cbop/cboz block-size device-tree properties to avoid inconsistency.
> +	 */
> +	if (riscv_cbom_block_size != 64 ||
> +	    riscv_cbop_block_size != 64 ||
> +	    riscv_cboz_block_size != 64) {

[Severity: Medium]
Will this check erroneously disable Zic64b if a platform does not implement
all three CBO extensions?

If a hardware platform implements Zic64b but omits an optional extension
like Zicbop, the riscv,cbop-block-size property might be absent from the
device tree, leaving riscv_cbop_block_size initialized at 0.

This unconditional check evaluates 0 != 64 as true, which would spuriously
trigger this error path and disable the valid Zic64b extension.

Should this validation only enforce the 64-byte size if the corresponding
block size variable is non-zero, indicating the extension is actually present?

> +		pr_err("Zic64b detected in ISA string, disabling as the cache block size is not 64 bytes\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260603-rva23u64-hwprobe-v2-v3-0-5529a7b28384@gmail.com?part=8