From: sashiko-bot@kernel.org
To: "Guodong Xu" <docular.xu@gmail.com>
Cc: devicetree@vger.kernel.org, kvm@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v3 07/15] dt-bindings: riscv: Add Zic64b extension description
Date: Tue, 02 Jun 2026 23:28:58 +0000 [thread overview]
Message-ID: <20260602232859.3494A1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260603-rva23u64-hwprobe-v2-v3-7-5529a7b28384@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The new `zic64b` extension is inserted out of alphabetical order, violating the explicit sorting rule defined in the file. The file requires multi-letter standard extensions to be sorted alphanumerically (see the comment `# multi-letter extensions, sorted alphanumerically`). Alphabetically, `zic64b` should be placed before `ziccamoa` (since '6' comes before 'c' in ASCII). However, the patch inserts it between `zkt` and `zicbom`. While it is correctly sorted relative to `zicbom` ('6' < 'b'), it propagates the pre-existing error of the cache-block extensions being incorrectly placed after the `Zk*` extensions, resulting in `zic64b` being placed at the wrong global alphanumeric position.
--
commit a825e53560db8497b83c2f594f48fa677434d00f
Author: Guodong Xu <docular.xu@gmail.com>
dt-bindings: riscv: Add Zic64b extension description
This commit adds the Zic64b extension to the RISC-V ISA extensions binding.
It defines the description for the extension and updates the schema to
enforce a block size of 64 for cbom, cbop, and cboz when Zic64b is present.
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 2b0a8a93bb214..ec1c9473d4256 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -590,6 +590,12 @@ properties:
> in version 1.0 of RISC-V Cryptography Extensions Volume I
> specification.
>
> + - const: zic64b
> + description:
> + The standard Zic64b extension for 64-byte naturally aligned cache
> + blocks, as ratified in RISC-V Profiles Version 1.0, with commit
> + b1d806605f87 ("Updated to ratified state.")
[Severity: Low]
This isn't a bug, but should this new entry be placed higher up in the list?
The properties block requires multi-letter extensions to be sorted
alphanumerically. Because '6' comes before 'c', would it be more accurate to
place zic64b before ziccamoa?
Does it make sense to place zic64b in its strictly correct alphanumeric
position, rather than continuing the out-of-order grouping of the existing
cache-block extensions like zicbom?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260603-rva23u64-hwprobe-v2-v3-0-5529a7b28384@gmail.com?part=7
next prev parent reply other threads:[~2026-06-02 23:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-03 11:11 [PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-06-03 11:11 ` [PATCH v3 01/15] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-06-03 11:11 ` [PATCH v3 02/15] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-06-03 11:11 ` [PATCH v3 03/15] riscv: Standardize extension capitalization Guodong Xu
2026-06-03 11:11 ` [PATCH v3 04/15] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-06-03 11:12 ` [PATCH v3 05/15] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 06/15] riscv: Add B to hwcap " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 07/15] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-06-02 23:28 ` sashiko-bot [this message]
2026-06-03 11:12 ` [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-06-02 23:28 ` sashiko-bot
2026-06-03 11:12 ` [PATCH v3 09/15] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-06-03 11:12 ` [PATCH v3 10/15] riscv: dts: spacemit: k1: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 11/15] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 12/15] riscv: Add a getter for user PMLEN support Guodong Xu
2026-06-03 11:12 ` [PATCH v3 13/15] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-06-02 23:37 ` sashiko-bot
2026-06-03 11:12 ` [PATCH v3 14/15] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-06-03 11:12 ` [PATCH v3 15/15] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
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