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From: sashiko-bot@kernel.org
To: "Michal Simek" <michal.simek@amd.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern
Date: Wed, 03 Jun 2026 15:24:46 +0000	[thread overview]
Message-ID: <20260603152446.C5DF71F00893@smtp.kernel.org> (raw)
In-Reply-To: <5662c24a9e65310fc6520afc95f1a639fe6d221e.1780499520.git.michal.simek@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The updated regex pattern fails to strictly constrain the MIO index to 00..77 due to the `+` quantifier and `.*$` wildcard.
--

commit 1ce5272f4b64f82cb19e5c321c26383c8c4fc25b
Author: Michal Simek <michal.simek@amd.com>

dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern

This commit attempts to fix the clock-names pattern to enforce a two-digit
decimal range constraint for MIO indices from 00 to 77. It replaces a broken
character class with an explicit alternation.

> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> index bef109d163a82..d843d95801b5f 100644
> --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -116,7 +116,7 @@ allOf:
>              - const: pss_alt_ref_clk
>              - const: aux_ref_clk
>              - const: gt_crx_ref_clk
> -            - pattern: "^mio_clk[00-77]+.*$"
> +            - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$"

[Severity: Medium]
The commit message states the intent is to constrain the MIO index
to the valid range 00..77.

However, the + quantifier applies to the entire alternation group, allowing
repetitions of two-digit numbers like mio_clk0011.

Additionally, the .*$ wildcard matches any trailing characters, meaning a
string like mio_clk0799 passes validation because 07 matches the group
and 99 is consumed by .*$.

Does this introduce a regression where the schema silently accepts invalid
clock names?

>              - pattern: "gem[0-3]+_emio_clk.*$"
>              - pattern: "swdt[0-1]+_ext_clk.*$"

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1780499520.git.michal.simek@amd.com?part=2

  reply	other threads:[~2026-06-03 15:24 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03 15:12 [PATCH v3 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Michal Simek
2026-06-03 15:12 ` [PATCH v3 1/5] dt-bindings: firmware: xilinx: Add missing example for ZynqMP Michal Simek
2026-06-03 15:30   ` Conor Dooley
2026-06-03 15:12 ` [PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern Michal Simek
2026-06-03 15:24   ` sashiko-bot [this message]
2026-06-03 15:33   ` Conor Dooley
2026-06-03 15:35     ` Michal Simek
2026-06-03 16:08       ` Conor Dooley
2026-06-03 15:12 ` [PATCH v3 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema Michal Simek
2026-06-03 15:34   ` sashiko-bot
2026-06-03 15:34   ` Conor Dooley
2026-06-03 15:12 ` [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Michal Simek
2026-06-03 15:12 ` [PATCH v3 5/5] arm64: versal-net: Switch Versal NET to firmware clock interface Michal Simek
2026-06-03 15:47   ` sashiko-bot

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