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From: sashiko-bot@kernel.org
To: "Joel Stanley" <joel@jms.id.au>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 7/7] riscv: dts: tenstorrent: Add Atlantis platform
Date: Thu, 04 Jun 2026 14:50:15 +0000	[thread overview]
Message-ID: <20260604145015.83A071F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260604143957.668047-8-joel@jms.id.au>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree assigns `CLK_RCPU_ROOT` as its own parent, creating an invalid cyclic clock dependency.
--

commit edef4717eb8086a5ba285a43a4a322f90272540a
Author: Joel Stanley <joel@jms.id.au>

riscv: dts: tenstorrent: Add Atlantis platform

Add initial support for the Tenstorrent Atlantis platform, based on the
Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.

[ ... ]

> diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
> new file mode 100644
> index 0000000000000..2513f0dcc62e5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi

[ ... ]

> +		prcm_rcpu: clock-controller@d0000000 {
> +			compatible = "tenstorrent,atlantis-prcm-rcpu";
> +			reg = <0x00 0xd0000000 0x00 0x10000>;
> +			clocks = <&osc_24m>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			assigned-clocks = <&prcm_rcpu CLK_RCPU_ROOT>, <&prcm_rcpu CLK_NOCC_CLK>;
> +			assigned-clock-parents = <&prcm_rcpu CLK_RCPU_ROOT>,
> +						 <&prcm_rcpu CLK_NOC_PLL>;

[Severity: Medium]
Does this configuration intentionally set CLK_RCPU_ROOT as its own parent?

The assigned-clocks property specifies <&prcm_rcpu CLK_RCPU_ROOT> as its
first entry, and the corresponding mapped entry in assigned-clock-parents
is also <&prcm_rcpu CLK_RCPU_ROOT>.

This instructs the Common Clock Framework to set the clock's parent to itself.
The CCF does not support self-parenting and will return an error or trigger
cycle detection warnings, preventing proper clock initialization. Is it possible
an external oscillator or upstream PLL was intended as the parent here?

> +		};

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260604143957.668047-1-joel@jms.id.au?part=7

  reply	other threads:[~2026-06-04 14:50 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-04 14:39 [PATCH v2 0/7] riscv: dts: tenstorrent: Add Atlantis platform Joel Stanley
2026-06-04 14:39 ` [PATCH v2 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible Joel Stanley
2026-06-04 14:39 ` [PATCH v2 2/7] dt-bindings: imsics: " Joel Stanley
2026-06-04 16:44   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon Joel Stanley
2026-06-04 16:44   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings Joel Stanley
2026-06-04 14:51   ` sashiko-bot
2026-06-04 16:43   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 5/7] dt-bindings: riscv: add Smrnmi extension description Joel Stanley
2026-06-04 14:39 ` [PATCH v2 6/7] dt-bindings: riscv: Add Tenstorrent Atlantis platform Joel Stanley
2026-06-04 16:43   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 7/7] riscv: dts: tenstorrent: Add " Joel Stanley
2026-06-04 14:50   ` sashiko-bot [this message]
2026-06-04 16:47   ` Conor Dooley

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