Re: [PATCH v2 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Conor Dooley <conor@kernel.org>]

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On Fri, Jun 05, 2026 at 12:09:50AM +0930, Joel Stanley wrote:
> The mtimer hardware is described in The RISC-V Instruction Set Manual,
> Volume II Privileged Architecture, 3.2.1. Machine Timer (mtime and
> mtimecmp) Registers.
> 
> The ACLINT was a standalone spec that made it to v1.0-rc4, but was never
> ratified. As explained by Anup:
> 
> > Only the timer defined by ACLINT specification is relevant but the
> > RISC-V privileged specification already provides a high-level
> > definition of mtime and mtimecmp MMIO registers (see section "Machine
> > Timer (mtime and mtimecmp) Registers").
> >
> > Due to the above reasons, we dropped our plans to ratify ACLINT
> > specification in-favor of AIA IMSIC and RISC-V Privileged
> > specification.
> 
> Link: https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v2:
>  - Use priv spec as reference
>  - Add soc name to tenstorrent compatible
>  - Fix reg property description
> ---
>  MAINTAINERS                                   |  1 +
>  .../bindings/timer/riscv,aclint-mtimer.yaml   | 56 +++++++++++++++++++
>  2 files changed, 57 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2fb1c75afd16..43dd9873bbc5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -23005,6 +23005,7 @@ M:	Joel Stanley <jms@oss.tenstorrent.com>
>  L:	linux-riscv@lists.infradead.org
>  S:	Maintained
>  T:	git https://github.com/tenstorrent/linux.git
> +F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>  F:	Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
>  F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
>  F:	arch/riscv/boot/dts/tenstorrent/
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..1d645570b191
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Advanced Core Local Interruptor (ACLINT) Machine-level Timer
> +
> +maintainers:
> +  - Joel Stanley <jms@oss.tenstorrent.com>
> +
> +description:
> +  The RISC-V machine-level timer exposes the memory-mapped mtime and per-hart
> +  mtimecmp registers defined in The RISC-V Instruction Set Manual, Volume II
> +  Privileged Architecture, 3.2.1. Machine Timer (mtime and mtimecmp) Registers.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - tenstorrent,atlantis-aclint-mtimer
> +          - qemu,aclint-mtimer
> +      - const: riscv,aclint-mtimer

Guess your v3 beat my reply to v2, but what I didn't want was the
riscv,aclint-mtimer compatible not the reference to the spec that you
actually implemented.
pw-bot: changes-requested

And that reminded me, there's a thead,c900-aclint-mtimer binding already
in the kernel, can't you piggy-back off that file instead of making a
new one?

Cheers,
Conor.

> +
> +  reg:
> +    items:
> +      - description: MTIMECMP registers, one per hart
> +      - description: MTIME register
> +
> +  reg-names:
> +    items:
> +      - const: mtimecmp
> +      - const: mtime
> +
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    timer@ac000000 {
> +      compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
> +      reg = <0xac000000 0x8000>, <0xac008000 0x8000>;
> +      reg-names = "mtimecmp", "mtime";
> +      interrupts-extended = <&cpu1intc 7>,
> +                            <&cpu2intc 7>,
> +                            <&cpu3intc 7>,
> +                            <&cpu4intc 7>;
> +    };
> +...
> -- 
> 2.47.3
> 

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