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From: sashiko-bot@kernel.org
To: "Joel Stanley" <joel@jms.id.au>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings
Date: Thu, 04 Jun 2026 14:51:51 +0000	[thread overview]
Message-ID: <20260604145152.526DD1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260604143957.668047-5-joel@jms.id.au>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The `reg` and `reg-names` properties implicitly require exactly two items, preventing configurations with a shared or external `mtime` register.
- [Low] The `interrupts-extended` and `reg-names` properties are missing from the `required` list in the RISC-V ACLINT MTIMER devicetree binding.
--

commit 1c0856d0470ac7f69215cb07bf901304f4595567
Author: Joel Stanley <joel@jms.id.au>

dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

This commit introduces the device tree binding for the RISC-V machine-level
timer (MTIMER). It supports configuring the memory-mapped mtime and per-hart
mtimecmp registers.

Link: https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435

> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 0000000000000..1d645570b1914
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

[ ... ]

> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - tenstorrent,atlantis-aclint-mtimer
> +          - qemu,aclint-mtimer
> +      - const: riscv,aclint-mtimer
> +
> +  reg:
> +    items:
> +      - description: MTIMECMP registers, one per hart
> +      - description: MTIME register

[Severity: Medium]
The RISC-V ACLINT specification allows the mtime register to be shared across
multiple MTIMER devices. By defining the reg array with two items, does this
schema implicitly enforce exactly two items, preventing configurations where
mtime is shared or external?

Should this include a minItems constraint to support secondary MTIMER devices
that only implement the mtimecmp region?

> +
> +  reg-names:
> +    items:
> +      - const: mtimecmp
> +      - const: mtime

[Severity: Medium]
Similarly, does this implicitly require exactly two names, which would
incorrectly reject device trees that lack a dedicated mtime region?

> +
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +
> +required:
> +  - compatible
> +  - reg

[Severity: Low]
Should interrupts-extended and reg-names be included in this required list?

Because the MTIMER hardware relies on timer interrupts to signal events to
the harts, omitting interrupts-extended allows device tree nodes to pass
schema validation without specifying how timer events are routed. Would this
result in a non-functional device passing validation?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260604143957.668047-1-joel@jms.id.au?part=4

  reply	other threads:[~2026-06-04 14:51 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-04 14:39 [PATCH v2 0/7] riscv: dts: tenstorrent: Add Atlantis platform Joel Stanley
2026-06-04 14:39 ` [PATCH v2 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible Joel Stanley
2026-06-04 14:39 ` [PATCH v2 2/7] dt-bindings: imsics: " Joel Stanley
2026-06-04 16:44   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon Joel Stanley
2026-06-04 16:44   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings Joel Stanley
2026-06-04 14:51   ` sashiko-bot [this message]
2026-06-04 16:43   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 5/7] dt-bindings: riscv: add Smrnmi extension description Joel Stanley
2026-06-04 14:39 ` [PATCH v2 6/7] dt-bindings: riscv: Add Tenstorrent Atlantis platform Joel Stanley
2026-06-04 16:43   ` Conor Dooley
2026-06-04 14:39 ` [PATCH v2 7/7] riscv: dts: tenstorrent: Add " Joel Stanley
2026-06-04 14:50   ` sashiko-bot
2026-06-04 16:47   ` Conor Dooley

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