Re: [PATCH v4 05/14] arm64: dts: st: add ltdc pins for stm32mp25

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The LTDC pixel clock pin (`LCD_CLK`) is configured with the lowest slew rate, which is insufficient for the 27 MHz pixel clock required by the panel, resulting in display signal corruption.
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commit de5f7f89d005f509af18ad70e07e79ff7c7c79aa
Author: Dario Binacchi <dario.binacchi@amarulasolutions.com>

arm64: dts: st: add ltdc pins for stm32mp25

This commit adds the LTDC pins used on the MicroGEA-STM32MP257-RMM board.

> diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
> --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
[ ... ]
> +	/omit-if-no-ref/
> +	ltdc_pins_a: ltdc-0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('C',  6, AF14)>, /* LCD_CLK */
[ ... ]
> +				 <STM32_PINMUX('F',  5, AF13)>, /* LCD_B6 */
> +				 <STM32_PINMUX('I',  4, AF13)>; /* LCD_B7 */
> +			bias-disable;
> +			drive-push-pull;
> +			slew-rate = <0>;

[Severity: High]
Does configuring slew-rate to 0 for all pins, including LCD_CLK, restrict
the signal bandwidth too heavily?

In the STM32 pinctrl driver, a slew-rate of 0 configures the pin for
low-speed output (typically designed for 2 MHz or less). Since the
MicroGEA-STM32MP257-RMM board uses a panel that requires a 27 MHz pixel
clock, will outputting this clock through a low-speed pin degrade signal
integrity and cause timing violations at the display driver?

Perhaps LCD_CLK should be separated into its own pin configuration block
with a higher slew rate to support the 27 MHz clock requirement.

> +		};
> +	};

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Sashiko AI review · https://sashiko.dev/#/patchset/20260605121957.78409-1-dario.binacchi@amarulasolutions.com?part=5