Re: [PATCH v4 12/14] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect pin configuration: SDMMC2_CK clock pin has an internal pull-up enabled.
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commit fada9dbb1e96d8d94231f0ac172f10f4898d55c5
Author: Dario Binacchi <dario.binacchi@amarulasolutions.com>
arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM

Support Engicam MicroGEA-STM32MP257 SoM with 8 GB eMMC Flash and 2 GB LPDDR4
DRAM.

> diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
> new file mode 100644
> index 0000000000000..5b4287e86deff
> --- /dev/null
> +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi

[ ... ]

> +&sdmmc2 {
> +	pinctrl-names = "default", "opendrain", "sleep";
> +	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> +	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
> +	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
> +	non-removable;
> +	no-sd;
> +	no-sdio;
> +	st,neg-edge;
> +	bus-width = <8>;
> +	vmmc-supply = <&scmi_v3v3>;
> +	vqmmc-supply = <&scmi_vddio2>;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;

[Severity: High]
Does this pin configuration cause signal integrity issues for the eMMC clock?

The referenced pin groups sdmmc2_b4_pins_a and sdmmc2_b4_od_pins_a in
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi configure the SDMMC2_CK clock
pin with an internal pull-up enabled instead of disabled:

arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi:
	sdmmc2_b4_pins_a {
		...
		pins2 {
			pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
			slew-rate = <2>;
			drive-push-pull;
			bias-pull-up;
		};
	};

Enabling an internal pull-up resistor on a high-speed continuous clock line
driven in push-pull mode can degrade signal integrity by altering the falling
edge and duty cycle.

This is particularly critical here because the eMMC is configured for
mmc-hs200-1_8v mode, which runs at up to 200MHz. The degraded signal can lead
to timing violations, eMMC enumeration failures, CRC errors, or subtle data
corruption.

> +	status = "okay";
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605121957.78409-1-dario.binacchi@amarulasolutions.com?part=12