Re: [PATCH net-next v2 14/14] arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCA8081 phy

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] The Ethernet PHY reset GPIO is incorrectly specified as 'snps,reset' within the PHY node, meaning it will never be acquired or toggled.
- [Low] The PCI endpoint nodes (`pci@0,0` and `pci@0,1`) incorrectly include bridge-exclusive properties.

Pre-existing issues:
- [High] The newly added `tc9564_gpio0` devicetree node will be rejected by its backing PCI driver due to a typo in the driver codebase.
--

commit 68b46926b348f5281d4dc4e8d117989c980cbff5
Author: Daniel Thompson <daniel@riscstar.com>

arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCA8081 phy

This commit adds device tree properties to support the TC9564 Ethernet bridge
and QCA8081 PHY on the QCS6490 RB3Gen2 platform. It describes how the
embedded PCIe endpoints, GPIO controller, and Ethernet PHYs are connected.

> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index e393ccf1884af..1d83b07360a33 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
[ ... ]
> @@ -938,19 +947,51 @@ pcie@3,0 {
>  			bus-range = <0x5 0xff>;
>  
>  			pci@0,0 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50000 0x0 0x0 0x0 0x0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				device_type = "pci";
>  				ranges;

[Severity: Low]
Does this endpoint node incorrectly include bridge-exclusive properties?

Properties like device_type = "pci", ranges, #address-cells, and #size-cells
are typically reserved for PCI bridges that enumerate child buses, not for
leaf endpoints.

> +
> +				tc9564_gpio0: gpio {
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +				};

[Severity: High]
This is a pre-existing issue, but the existing PCI MFD driver for this
endpoint has a typo that will cause it to reject this node.

Looking at dev_node_child_gpio() in drivers/misc/tc956x_pci.c, the driver
explicitly checks for "gpio-controllerX":

if (!of_property_present(np, "gpio-controllerX"))
    dev_err(dev, "gpio node contains no gpio-contrller property\n");

Because this patch correctly uses "gpio-controller", will the driver fail
to instantiate the controller and prevent the PHY reset line from being
driven?

>  			};
>  
>  			pci@0,1 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50100 0x0 0x0 0x0 0x0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				device_type = "pci";
>  				ranges;

[Severity: Low]
Are the bridge-exclusive properties (device_type, ranges, #address-cells)
also incorrectly applied to this leaf endpoint node?

> +
> +				ethernet {
> +					phy-mode = "sgmii";
> +					phy-handle = <&tc9564_emac1_phy>;
> +
> +					mdio {
> +						compatible = "snps,dwmac-mdio";
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +
> +						tc9564_emac1_phy: ethernet-phy@1c {
> +							compatible = "ethernet-phy-id004d.d101";
> +							reg = <0x1c>;
> +							snps,reset = <&tc9564_gpio0 1 GPIO_ACTIVE_LOW>;

[Severity: High]
Will this reset GPIO ever be acquired or toggled during initialization?

The stmmac_mdio_reset() function looks for the "snps,reset" GPIO on the
MAC's device node (ethernet), but it is placed here in the PHY subnode.
Meanwhile, the standard mdio_device_register_reset() function looks for
"reset-gpios" in the PHY node, not "snps,reset".

Since neither subsystem will find this property, it seems the PHY reset
will not be performed. Should this either be renamed to "reset-gpios" or
moved to the MAC node?

> +							reset-assert-us = <11000>;
> +							reset-deassert-us = <70000>;
> +
> +							vdd18-supply = <&qep_1p8>;
> +
> +							pinctrl-names = "default";
> +							pinctrl-0 = <&qep_irq_pin>;
> +							interrupts-extended = <&tlmm 101 IRQ_TYPE_LEVEL_LOW>;
> +						};
> +					};
> +				};
>  			};
>  		};
>  	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605010022.968612-1-elder@riscstar.com?part=14