* [PATCH 0/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI and FRAM @ 2026-06-12 8:03 Wolfram Sang 2026-06-12 8:03 ` [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers Wolfram Sang 2026-06-12 8:03 ` [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Wolfram Sang 0 siblings, 2 replies; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 8:03 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Conor Dooley, devicetree, Geert Uytterhoeven, Krzysztof Kozlowski, Magnus Damm, Rob Herring Here are the patches to enable the SPI-FRAM with FIFO (no DMA yet, needs more work) on the RZ/N1D Extension board. Wolfram Sang (2): ARM: dts: renesas: r9a06g032: Describe SPI controllers ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM .../dts/renesas/r9a06g032-rzn1d400-eb.dts | 25 ++++++ arch/arm/boot/dts/renesas/r9a06g032.dtsi | 90 +++++++++++++++++++ 2 files changed, 115 insertions(+) -- 2.47.3 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers 2026-06-12 8:03 [PATCH 0/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI and FRAM Wolfram Sang @ 2026-06-12 8:03 ` Wolfram Sang 2026-06-12 8:16 ` sashiko-bot 2026-06-12 8:25 ` Geert Uytterhoeven 2026-06-12 8:03 ` [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Wolfram Sang 1 sibling, 2 replies; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 8:03 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree Add nodes for the 6 SPI controllers of the Renesas RZ/N1D SoC. The first 4 can only be controllers, the latter 2 can only be targets. DMA nodes are not added yet because DMA needs some extra code in the drivers and cannot be tested yet. Basic FIFO mode works reliably, though. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 90 ++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 442ea26b40f5..e5c76b38a58e 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -563,6 +563,96 @@ gic: interrupt-controller@44101000 { <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + /* Controller only */ + spi1: spi@50005000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50005000 0x200>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Controller only */ + spi2: spi@50006000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50006000 0x200>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI1>, <&sysctrl R9A06G032_HCLK_SPI1>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Controller only */ + spi3: spi@50007000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50007000 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI2>, <&sysctrl R9A06G032_HCLK_SPI2>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Controller only */ + spi4: spi@50008000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50008000 0x200>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI3>, <&sysctrl R9A06G032_HCLK_SPI3>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Target only */ + spi5: spi@50009000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50009000 0x200>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Target only */ + spi6: spi@5000a000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x5000a000 0x200>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-max-frequency = <12500000>; + num-cs = <1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + /* * The GPIO mapping to the corresponding pins is not obvious. * See the hardware documentation for details. -- 2.47.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers 2026-06-12 8:03 ` [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers Wolfram Sang @ 2026-06-12 8:16 ` sashiko-bot 2026-06-12 8:21 ` Wolfram Sang 2026-06-12 8:25 ` Geert Uytterhoeven 1 sibling, 1 reply; 9+ messages in thread From: sashiko-bot @ 2026-06-12 8:16 UTC (permalink / raw) To: Wolfram Sang; +Cc: devicetree, conor+dt, robh, wsa+renesas Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Target-only SPI controllers missing the `spi-slave` property and improperly configured as hosts. - [Low] The `spi-max-frequency` property is improperly placed on SPI controller nodes. -- commit 812adfb1b6b8e7de5a970209c3fa9a2a938214f8 Author: Wolfram Sang <wsa+renesas@sang-engineering.com> ARM: dts: renesas: r9a06g032: Describe SPI controllers This commit adds device tree nodes for the six SPI controllers on the Renesas RZ/N1D SoC. The first four controllers are configured as hosts, while the remaining two are designated as targets. > diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > index 442ea26b40f53..e5c76b38a58e4 100644 > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > @@ -563,6 +563,96 @@ gic: interrupt-controller@44101000 { > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + /* Controller only */ > + spi1: spi@50005000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x50005000 0x200>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; [Severity: Low] Does the spi-max-frequency property belong on the controller node? According to the SPI bindings, spi-max-frequency is meant to specify the maximum operating frequency of an SPI peripheral child node, rather than the controller itself. Setting it on the controller node might be ignored by the driver and could trigger dtbs_check warnings. This same pattern appears to be repeated for spi2 through spi6. > + num-cs = <4>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; [ ... ] > + /* Target only */ > + spi5: spi@50009000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x50009000 0x200>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; > + num-cs = <1>; > + status = "disabled"; > + #address-cells = <1>; [Severity: High] Since this node is designated as "Target only", should it include the spi-slave boolean property? Without spi-slave, the DesignWare SPI core driver evaluates device_property_read_bool(dev, "spi-slave") as false and unconditionally configures the hardware as an SPI host. This would cause the controller to incorrectly attempt to drive the SCK and CS lines. Additionally, standard SPI slave bindings expect #address-cells = <0> and generally do not use the num-cs property for slave nodes. > + #size-cells = <0>; > + }; > + > + /* Target only */ > + spi6: spi@5000a000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x5000a000 0x200>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; > + num-cs = <1>; > + status = "disabled"; > + #address-cells = <1>; [Severity: High] Is this node missing the spi-slave property as well? Similar to the spi5 node, omitting spi-slave will cause the core driver to configure this as a host instead of a target. The num-cs and #address-cells properties here also appear to violate standard target node bindings. > + #size-cells = <0>; > + }; -- Sashiko AI review · https://sashiko.dev/#/patchset/20260612080354.57459-4-wsa+renesas@sang-engineering.com?part=1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers 2026-06-12 8:16 ` sashiko-bot @ 2026-06-12 8:21 ` Wolfram Sang 0 siblings, 0 replies; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 8:21 UTC (permalink / raw) To: sashiko-reviews, linux-renesas-soc; +Cc: devicetree, conor+dt, robh [-- Attachment #1: Type: text/plain, Size: 395 bytes --] On Fri, Jun 12, 2026 at 08:16:30AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [High] Target-only SPI controllers missing the `spi-slave` property and improperly configured as hosts. > - [Low] The `spi-max-frequency` property is improperly placed on SPI controller nodes. Sounds reasonable, will check! [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers 2026-06-12 8:03 ` [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers Wolfram Sang 2026-06-12 8:16 ` sashiko-bot @ 2026-06-12 8:25 ` Geert Uytterhoeven 2026-06-12 18:43 ` Wolfram Sang 1 sibling, 1 reply; 9+ messages in thread From: Geert Uytterhoeven @ 2026-06-12 8:25 UTC (permalink / raw) To: Wolfram Sang Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree Hi Wolfram, On Fri, 12 Jun 2026 at 10:04, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Add nodes for the 6 SPI controllers of the Renesas RZ/N1D SoC. The first > 4 can only be controllers, the latter 2 can only be targets. DMA nodes > are not added yet because DMA needs some extra code in the drivers and > cannot be tested yet. Basic FIFO mode works reliably, though. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > @@ -563,6 +563,96 @@ gic: interrupt-controller@44101000 { > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + /* Controller only */ > + spi1: spi@50005000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x50005000 0x200>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; That is 12.5 MHz (for all controllers). According to Table 3.2, the maximum SPI reference clock frequency depends on the instance: - spi1: 125 MHz, - spi2: 62.5 MHz, - spi3: 31.25 MHz, - spi4: 15.625 MHz. As the minimum divider is 2, spi-max-frequency must be half of the reference clock. However, spi-max-frequency also depends on the target device(s), and on board wiring, so typically it is overridden or set in board DTS. > + num-cs = <4>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + /* Target only */ > + spi5: spi@50009000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x50009000 0x200>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; spi-max-frequency doe snot make sense for a target-only controller. > + num-cs = <1>; > + status = "disabled"; > + #address-cells = <1>; <0> > + #size-cells = <0>; Missing "spi-slave" > + }; > + > + /* Target only */ > + spi6: spi@5000a000 { > + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; > + reg = <0x5000a000 0x200>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>; > + clock-names = "ssi_clk", "pclk"; > + power-domains = <&sysctrl>; > + spi-max-frequency = <12500000>; > + num-cs = <1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; Likewise > + }; > + > /* > * The GPIO mapping to the corresponding pins is not obvious. > * See the hardware documentation for details. The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers 2026-06-12 8:25 ` Geert Uytterhoeven @ 2026-06-12 18:43 ` Wolfram Sang 0 siblings, 0 replies; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 18:43 UTC (permalink / raw) To: Geert Uytterhoeven Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree [-- Attachment #1: Type: text/plain, Size: 248 bytes --] > However, spi-max-frequency also depends on the target device(s), > and on board wiring, so typically it is overridden or set in board DTS. I'll drop them all! Everything else is accepted, too, and already fixed. Also put "disabled" last now. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM 2026-06-12 8:03 [PATCH 0/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI and FRAM Wolfram Sang 2026-06-12 8:03 ` [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers Wolfram Sang @ 2026-06-12 8:03 ` Wolfram Sang 2026-06-12 8:47 ` Geert Uytterhoeven 1 sibling, 1 reply; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 8:03 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree Activate the FRAM and the SPI bus which it is attached to. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- .../dts/renesas/r9a06g032-rzn1d400-eb.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index 97a339b30d76..ead379988fb1 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -53,6 +53,10 @@ led@1 { }; }; +&gpio2 { + status = "okay"; +}; + &i2c2 { /* Sensors are different across revisions. All are LM75B compatible */ sensor@49 { @@ -152,6 +156,13 @@ pins_sdio1_clk: pins-sdio1-clk { drive-strength = <12>; }; + pins_spi1: pins-spi1 { + pinmux = <RZN1_PINMUX(156, RZN1_FUNC_SPI0_M)>, + <RZN1_PINMUX(157, RZN1_FUNC_SPI0_M)>, + <RZN1_PINMUX(158, RZN1_FUNC_SPI0_M)>, + <RZN1_PINMUX(159, RZN1_FUNC_GPIO)>; + }; + pins_uart2: pins-uart2 { pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>, <RZN1_PINMUX(106, RZN1_FUNC_UART2)>, @@ -168,6 +179,20 @@ &sdio1 { status = "okay"; }; +&spi1 { + pinctrl-0 = <&pins_spi1>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>; + + fram: fram@0 { + compatible = "cypress,fm25", "atmel,at25"; + reg = <0>; + spi-max-frequency = <12500000>; + }; +}; + &switch { pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; -- 2.47.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM 2026-06-12 8:03 ` [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Wolfram Sang @ 2026-06-12 8:47 ` Geert Uytterhoeven 2026-06-12 18:42 ` Wolfram Sang 0 siblings, 1 reply; 9+ messages in thread From: Geert Uytterhoeven @ 2026-06-12 8:47 UTC (permalink / raw) To: Wolfram Sang Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree Hi Wolfram, On Fri, 12 Jun 2026 at 10:04, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Activate the FRAM and the SPI bus which it is attached to. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts > +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts > @@ -152,6 +156,13 @@ pins_sdio1_clk: pins-sdio1-clk { > drive-strength = <12>; > }; > > + pins_spi1: pins-spi1 { > + pinmux = <RZN1_PINMUX(156, RZN1_FUNC_SPI0_M)>, > + <RZN1_PINMUX(157, RZN1_FUNC_SPI0_M)>, > + <RZN1_PINMUX(158, RZN1_FUNC_SPI0_M)>, > + <RZN1_PINMUX(159, RZN1_FUNC_GPIO)>; > + }; > + > pins_uart2: pins-uart2 { > pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>, > <RZN1_PINMUX(106, RZN1_FUNC_UART2)>, > @@ -168,6 +179,20 @@ &sdio1 { > status = "okay"; > }; > > +&spi1 { > + pinctrl-0 = <&pins_spi1>; > + pinctrl-names = "default"; Please document that this depends on SW2-4 being OFF. > + status = "okay"; > + > + cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>; It doesn't work with hardware chip-select? > + > + fram: fram@0 { > + compatible = "cypress,fm25", "atmel,at25"; > + reg = <0>; > + spi-max-frequency = <12500000>; The actual FRAM part seems to support 40 MHz, but that may be limited by the board wiring. > + }; > +}; > + > &switch { > pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, > <&pins_mdio1>; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM 2026-06-12 8:47 ` Geert Uytterhoeven @ 2026-06-12 18:42 ` Wolfram Sang 0 siblings, 0 replies; 9+ messages in thread From: Wolfram Sang @ 2026-06-12 18:42 UTC (permalink / raw) To: Geert Uytterhoeven Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree [-- Attachment #1: Type: text/plain, Size: 1288 bytes --] Hi Geert, thank you for the reviews! > > +&spi1 { > > + pinctrl-0 = <&pins_spi1>; > > + pinctrl-names = "default"; > > Please document that this depends on SW2-4 being OFF. Hmmm, this is a bit weird. SW2-4 does only do the routing to the SPI5 (target) controller connector. SPI1 is totally independent of that. I can read out the FRAM with 2-4 being ON. Dunno how well that behaves in parallel with RMII2 ;) Shall I still do the comment? > > + cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>; > > It doesn't work with hardware chip-select? I couldn't get it to work and I know other people also use cs-gpios on their custom boards. > > + fram: fram@0 { > > + compatible = "cypress,fm25", "atmel,at25"; > > + reg = <0>; > > + spi-max-frequency = <12500000>; > > The actual FRAM part seems to support 40 MHz, but that may > be limited by the board wiring. So, what do we do? In my tests, 40MHz did not work. Up to 30MHz it seems to work. However, all of the BSP DTS snippets say RZ/N1 can only do up to 12.5MHz. I don't have an errata documenting this nor could I find another source. I would still rather play safe here. I could add a comment, though. Happy hacking, Wolfram [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-06-12 18:43 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-12 8:03 [PATCH 0/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI and FRAM Wolfram Sang 2026-06-12 8:03 ` [PATCH 1/2] ARM: dts: renesas: r9a06g032: Describe SPI controllers Wolfram Sang 2026-06-12 8:16 ` sashiko-bot 2026-06-12 8:21 ` Wolfram Sang 2026-06-12 8:25 ` Geert Uytterhoeven 2026-06-12 18:43 ` Wolfram Sang 2026-06-12 8:03 ` [PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Wolfram Sang 2026-06-12 8:47 ` Geert Uytterhoeven 2026-06-12 18:42 ` Wolfram Sang
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