[PATCH] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516

[PATCH] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

According to the Jedec 5.1 specification, the device is held in reset
when RST_n is low, therefore the polarity of the line must be that, as
specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml).

Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162]
bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset
forever.

Cc: stable@vger.kernel.org
Fixes: 56198acdbf0d ("arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
PP-1516 is affected by the same issue that Cobra has and for which a
patch[1] has already been sent.

[1] https://lore.kernel.org/linux-rockchip/20260609081728.30616-2-jakobunt@gmail.com/
---
 arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
index 192791993f059..02200de695d31 100644
--- a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
@@ -33,7 +33,7 @@ emmc_pwrseq: emmc-pwrseq {
 		compatible = "mmc-pwrseq-emmc";
 		pinctrl-0 = <&emmc_reset>;
 		pinctrl-names = "default";
-		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
 	};
 
 	gpio-leds {

---
base-commit: 2b414a95b8f7307d42173ba9e580d6d3e2bcbfce
change-id: 20260612-pp1516-emmc-polarity-5a7fb54db917

Best regards,
--  
Quentin Schulz <quentin.schulz@cherry.de>

Re: [PATCH] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Incomplete fix: identical incorrect eMMC reset polarity (GPIO_ACTIVE_HIGH) remains in multiple PX30 boards.
--

commit 764233a2abb692d41607851c93d3fed45fcab940
Author: Quentin Schulz <quentin.schulz@cherry.de>

arm64: dts: rockchip: fix eMMC reset polarity on PP-1516

This commit fixes the eMMC reset polarity for the px30-pp1516 board by
changing it to GPIO_ACTIVE_LOW to comply with the Jedec 5.1 specification.
The previous GPIO_ACTIVE_HIGH polarity caused eMMC devices with specific
RST_n_FUNCTION bitfield settings to be held in reset forever.

> diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
> index 192791993f059..02200de695d31 100644
> --- a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
> @@ -33,7 +33,7 @@ emmc_pwrseq: emmc-pwrseq {
>  		compatible = "mmc-pwrseq-emmc";
>  		pinctrl-0 = <&emmc_reset>;
>  		pinctrl-names = "default";
> -		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;

[Severity: High]
This isn't a bug introduced by this patch, but does this same fix need to be
applied to other PX30 boards?

Looking at the tree, several other PX30 device trees still use the exact same
incorrect GPIO_ACTIVE_HIGH configuration for their emmc_pwrseq nodes:

arch/arm64/boot/dts/rockchip/px30-cobra.dtsi
arch/arm64/boot/dts/rockchip/px30-evb.dts
arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi

Will these boards also fail to boot if used with eMMC devices where the
RST_n_FUNCTION[162] bitfield is set to 0x1, or do they guarantee different
hardware behavior?

>  	};
>  
>  	gpio-leds {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260612-pp1516-emmc-polarity-v1-1-4816c1c909f7@cherry.de?part=1