* [PATCH] dt-bindings: sound: nvidia,tegra30-ahub: Convert to DT schema
@ 2026-06-13 8:24 Charan Pedumuru
2026-06-13 8:35 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Charan Pedumuru @ 2026-06-13 8:24 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter
Cc: linux-sound, devicetree, linux-tegra, linux-kernel,
Charan Pedumuru
Convert NVIDIA Tegra Audio Hub (AHUB) binding to DT schema.
The per-SoC differences in reset-names, dma-names, and reg entry
counts described in the text binding are now enforced via allOf
conditionals, making previously prose-only constraints machine
validatable.
Child node CIF ID properties are formally declared under
patternProperties to allow dtschema to validate i2s subnodes.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../bindings/sound/nvidia,tegra30-ahub.txt | 88 ------
.../bindings/sound/nvidia,tegra30-ahub.yaml | 299 +++++++++++++++++++++
2 files changed, 299 insertions(+), 88 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
deleted file mode 100644
index 0e9a1895d7fb..000000000000
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-NVIDIA Tegra30 AHUB (Audio Hub)
-
-Required properties:
-- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
- must contain "nvidia,tegra114-ahub". For Tegra124, must contain
- "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
- plus at least one of the above, where <chip> is tegra132.
-- reg : Should contain the register physical address and length for each of
- the AHUB's register blocks.
- - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
- - Tegra114 requires an additional entry, for the APBIF2 register block.
-- interrupts : Should contain AHUB interrupt
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- - d_audio
- - apbif
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- Tegra30 and later:
- - d_audio
- - apbif
- - i2s0
- - i2s1
- - i2s2
- - i2s3
- - i2s4
- - dam0
- - dam1
- - dam2
- - spdif
- Tegra114 and later additionally require:
- - amx
- - adx
- Tegra124 and later additionally require:
- - amx1
- - adx1
- - afc0
- - afc1
- - afc2
- - afc3
- - afc4
- - afc5
-- ranges : The bus address mapping for the configlink register bus.
- Can be empty since the mapping is 1:1.
-- dmas : Must contain an entry for each entry in clock-names.
- See ../dma/dma.txt for details.
-- dma-names : Must include the following entries:
- - rx0 .. rx<n>
- - tx0 .. tx<n>
- ... where n is:
- Tegra30: 3
- Tegra114, Tegra124: 9
-- #address-cells : For the configlink bus. Should be <1>;
-- #size-cells : For the configlink bus. Should be <1>.
-
-AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
-For RX CIFs, the numbers indicate the register number within AHUB routing
-register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
-For TX CIFs, the numbers indicate the bit position within the AHUB routing
-registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
-
-Example:
-
-ahub@70080000 {
- compatible = "nvidia,tegra30-ahub";
- reg = <0x70080000 0x200 0x70080200 0x100>;
- interrupts = < 0 103 0x04 >;
- nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 106>, <&tegra_car 107>;
- clock-names = "d_audio", "apbif";
- resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
- <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
- <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
- <&tegra_car 110>, <&tegra_car 10>;
- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
- "i2s3", "i2s4", "dam0", "dam1", "dam2",
- "spdif";
- dmas = <&apbdma 1>, <&apbdma 1>;
- <&apbdma 2>, <&apbdma 2>;
- <&apbdma 3>, <&apbdma 3>;
- <&apbdma 4>, <&apbdma 4>;
- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml
new file mode 100644
index 000000000000..82738058f672
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml
@@ -0,0 +1,299 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra30-ahub.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Audio Hub (AHUB)
+
+maintainers:
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+description:
+ The NVIDIA Tegra AHUB (Audio Hub) is an audio interconnect block used to
+ route data between various audio clients such as I2S, DAM, SPDIF, and
+ APBIF. It exposes multiple register regions and supports different
+ configurations depending on the Tegra SoC generation. The AHUB also
+ provides a configlink bus for child audio components, which use CIF
+ (Client Interface) IDs to identify their data paths. The number of DMA
+ channels, reset lines, and additional modules varies across Tegra30,
+ Tegra114, and Tegra124 platforms.
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra30-ahub
+ - const: nvidia,tegra114-ahub
+ - const: nvidia,tegra124-ahub
+ - items:
+ - const: nvidia,tegra132-ahub
+ - const: nvidia,tegra124-ahub
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Clock for the D_AUDIO domain
+ - description: Clock for the APBIF interface
+
+ clock-names:
+ items:
+ - const: d_audio
+ - const: apbif
+
+ resets:
+ minItems: 11
+ maxItems: 21
+
+ reset-names:
+ oneOf:
+ # Tegra30: d_audio apbif i2s0-4 dam0-2 spdif
+ - items:
+ - const: d_audio
+ - const: apbif
+ - const: i2s0
+ - const: i2s1
+ - const: i2s2
+ - const: i2s3
+ - const: i2s4
+ - const: dam0
+ - const: dam1
+ - const: dam2
+ - const: spdif
+
+ # Tegra114: adds amx adx
+ - items:
+ - const: d_audio
+ - const: apbif
+ - const: i2s0
+ - const: i2s1
+ - const: i2s2
+ - const: i2s3
+ - const: i2s4
+ - const: dam0
+ - const: dam1
+ - const: dam2
+ - const: spdif
+ - const: amx
+ - const: adx
+
+ # Tegra124: adds amx1 adx1 afc0-5
+ - items:
+ - const: d_audio
+ - const: apbif
+ - const: i2s0
+ - const: i2s1
+ - const: i2s2
+ - const: i2s3
+ - const: i2s4
+ - const: dam0
+ - const: dam1
+ - const: dam2
+ - const: spdif
+ - const: amx
+ - const: amx1
+ - const: adx
+ - const: adx1
+ - const: afc0
+ - const: afc1
+ - const: afc2
+ - const: afc3
+ - const: afc4
+ - const: afc5
+
+ dmas:
+ minItems: 8
+ maxItems: 20
+
+ dma-names:
+ oneOf:
+ # Tegra30: rx0..rx3 tx0..tx3 (n=3)
+ - items:
+ - const: rx0
+ - const: tx0
+ - const: rx1
+ - const: tx1
+ - const: rx2
+ - const: tx2
+ - const: rx3
+ - const: tx3
+
+ # Tegra114/124: rx0..rx9 tx0..tx9 (n=9)
+ - items:
+ - const: rx0
+ - const: tx0
+ - const: rx1
+ - const: tx1
+ - const: rx2
+ - const: tx2
+ - const: rx3
+ - const: tx3
+ - const: rx4
+ - const: tx4
+ - const: rx5
+ - const: tx5
+ - const: rx6
+ - const: tx6
+ - const: rx7
+ - const: tx7
+ - const: rx8
+ - const: tx8
+ - const: rx9
+ - const: tx9
+
+ "#address-cells":
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ "#size-cells":
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ ranges: true
+
+patternProperties:
+ "^i2s@[0-9a-f]+$":
+ type: object
+
+ allOf:
+ - $ref: /schemas/sound/nvidia,tegra30-i2s.yaml#
+
+ properties:
+ nvidia,ahub-cif-ids:
+ description: Pair of AHUB CIF IDs for the RX and TX data paths.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+
+ required:
+ - nvidia,ahub-cif-ids
+
+ unevaluatedProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra124-ahub
+ then:
+ properties:
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ resets:
+ minItems: 21
+ maxItems: 21
+
+ dmas:
+ minItems: 20
+ maxItems: 20
+
+ else:
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra30-ahub
+ then:
+ properties:
+ reg:
+ maxItems: 2
+
+ resets:
+ minItems: 11
+ maxItems: 11
+
+ dmas:
+ minItems: 8
+ maxItems: 8
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra114-ahub
+ then:
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ resets:
+ minItems: 13
+ maxItems: 13
+
+ dmas:
+ minItems: 20
+ maxItems: 20
+
+required:
+ - reg
+ - compatible
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - dmas
+ - dma-names
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/tegra30-car.h>
+ ahub@70080000 {
+ compatible = "nvidia,tegra30-ahub";
+ reg = <0x70080000 0x200>, <0x70080200 0x100>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+ <&tegra_car TEGRA30_CLK_APBIF>;
+ clock-names = "d_audio", "apbif";
+ resets = <&tegra_car 106>, <&tegra_car 107>,
+ <&tegra_car 30>, <&tegra_car 11>,
+ <&tegra_car 18>, <&tegra_car 101>,
+ <&tegra_car 102>, <&tegra_car 108>,
+ <&tegra_car 109>, <&tegra_car 110>,
+ <&tegra_car 10>;
+ reset-names = "d_audio", "apbif",
+ "i2s0", "i2s1", "i2s2", "i2s3", "i2s4",
+ "dam0", "dam1", "dam2",
+ "spdif";
+ dmas = <&apbdma 1>, <&apbdma 1>,
+ <&apbdma 2>, <&apbdma 2>,
+ <&apbdma 3>, <&apbdma 3>,
+ <&apbdma 4>, <&apbdma 4>;
+ dma-names = "rx0", "tx0", "rx1", "tx1",
+ "rx2", "tx2", "rx3", "tx3";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s@70080300 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080300 0x100>;
+ nvidia,ahub-cif-ids = <4 4>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+ resets = <&tegra_car 30>;
+ reset-names = "i2s";
+ };
+ };
+...
---
base-commit: db7efce4ae23ad5e42f5f55428f529ff62b86fab
change-id: 20260422-nvidia-ahub-d2ceb0372744
Best regards,
--
Charan Pedumuru <charan.pedumuru@gmail.com>
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] dt-bindings: sound: nvidia,tegra30-ahub: Convert to DT schema
2026-06-13 8:24 [PATCH] dt-bindings: sound: nvidia,tegra30-ahub: Convert to DT schema Charan Pedumuru
@ 2026-06-13 8:35 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-06-13 8:35 UTC (permalink / raw)
To: Charan Pedumuru; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `allOf` conditional block for `nvidia,tegra124-ahub` fails to constrain the `reg` property count, allowing missing register regions to silently pass validation.
--
commit 9a0f1d546144b78d414e177cfaf59f6770e9ba9b
Author: Charan Pedumuru <charan.pedumuru@gmail.com>
dt-bindings: sound: nvidia,tegra30-ahub: Convert to DT schema
Converts the NVIDIA Tegra Audio Hub (AHUB) binding from text to DT schema.
The patch enforces per-SoC differences in reset-names, dma-names, and reg
entry counts using allOf conditionals.
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml
> new file mode 100644
> index 0000000000000..82738058f6722
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.yaml
[ ... ]
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra124-ahub
> + then:
> + properties:
> + "#address-cells":
> + const: 2
[Severity: Low]
Does the tegra124-ahub conditional need to enforce the reg property count?
The commit message mentions that reg entry counts described in the text
binding are now enforced via allOf conditionals, but this block omits the
reg constraints for tegra124-ahub. It falls back to the top-level
minItems: 2, maxItems: 3, which could allow a tegra124-ahub node with only
2 register entries to incorrectly pass schema validation. Since tegra114-ahub
enforces minItems: 3 and maxItems: 3, should this block do the same?
> +
> + "#size-cells":
> + const: 2
> +
> + resets:
> + minItems: 21
> + maxItems: 21
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260613-nvidia-ahub-v1-1-5b7e85301736@gmail.com?part=1
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