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From: sashiko-bot@kernel.org
To: "Maulik Shah" <maulik.shah@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v3 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper
Date: Tue, 16 Jun 2026 09:36:23 +0000	[thread overview]
Message-ID: <20260616093623.936991F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260616-hamoa_pdc_v3-v3-3-4d8e1504ea75@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Uninitialized spinlock acquired during driver probe.
--

commit ff89675171bbba82a63beea5300191b24d1a290f
Author: Maulik Shah <maulik.shah@oss.qualcomm.com>

irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper

This commit removes the pdc_enable_intr() wrapper and moves its locking
into pdc_enable_intr_bank(), as the lock is only needed for the shared
bank and not for individual IRQ_CFG registers.

> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
> index b9acb0f25c9c8..6c556464d37c0 100644
> --- a/drivers/irqchip/qcom-pdc.c
> +++ b/drivers/irqchip/qcom-pdc.c
> @@ -206,6 +206,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
>  	index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
>  	mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
>  
> +	guard(raw_spinlock)(&pdc->lock);

[Severity: High]
Does this cause an uninitialized spinlock to be acquired during driver probe?

Looking at qcom_pdc_probe(), the lock is initialized after setting up the pin
mapping:

qcom_pdc_probe() {
    ...
    ret = pdc_setup_pin_mapping(dev, node);
    ...
    raw_spin_lock_init(&pdc->lock);
    ...
}

And pdc_setup_pin_mapping() invokes pdc->enable_intr() for each pin:

pdc_setup_pin_mapping() {
    ...
    for (int i = 0; i < pdc->region[n].cnt; i++)
        pdc->enable_intr(i + pdc->region[n].pin_base, 0);
    ...
}

Previously, pdc_setup_pin_mapping() bypassed the lock because it was held in
the pdc_enable_intr() wrapper, not the enable_intr() callback. By moving the
lock down into pdc_enable_intr_bank(), won't the probe sequence now attempt to
acquire a zero-initialized lock before it has been initialized with
raw_spin_lock_init()?

> +
>  	enable = pdc_reg_read(pdc->regs->irq_en_reg, index);
>  	__assign_bit(mask, &enable, on);
>  
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com?part=3

  reply	other threads:[~2026-06-16  9:36 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-16  9:25 [PATCH v3 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state Maulik Shah
2026-06-16  9:25 ` [PATCH v3 1/8] irqchip/qcom-pdc: restructure version support Maulik Shah
2026-06-16  9:25 ` [PATCH v3 2/8] irqchip/qcom-pdc: Move all statics to struct pdc_desc Maulik Shah
2026-06-16  9:25 ` [PATCH v3 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper Maulik Shah
2026-06-16  9:36   ` sashiko-bot [this message]
2026-06-16  9:25 ` [PATCH v3 4/8] irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI Maulik Shah
2026-06-16  9:25 ` [PATCH v3 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode Maulik Shah
2026-06-16  9:43   ` sashiko-bot
2026-06-16  9:25 ` [PATCH v3 6/8] pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller Maulik Shah
2026-06-16  9:45   ` sashiko-bot
2026-06-16  9:25 ` [PATCH v3 7/8] Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" Maulik Shah
2026-06-16  9:25 ` [PATCH v3 8/8] arm64: dts: qcom: x1e80100: Add deepest idle state Maulik Shah

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