[PATCH v2 1/9] dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5

[PATCH v2 1/9] dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5

[Tanmay Kathpalia]

Add COMBOPHY_RESET definition at index 38 for the combo PHY reset
control on Altera Agilex5 SoCs. This reset is used by peripherals
such as the SD/eMMC controller that share the combo PHY.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 include/dt-bindings/reset/altr,rst-mgr-s10.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
index 04c4d0c6fd34..c2505b9eb63e 100644
--- a/include/dt-bindings/reset/altr,rst-mgr-s10.h
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -22,7 +22,7 @@
 #define USB0_RESET		35
 #define USB1_RESET		36
 #define NAND_RESET		37
-/* 38 is empty */
+#define COMBOPHY_RESET		38
 #define SDMMC_RESET		39
 #define EMAC0_OCP_RESET		40
 #define EMAC1_OCP_RESET		41
-- 
2.43.7

Re: (subset) [PATCH v2 1/9] dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5

[Philipp Zabel]

On Sa, 2026-06-27 at 13:14 -0700, Tanmay Kathpalia wrote:
> Add COMBOPHY_RESET definition at index 38 for the combo PHY reset
> control on Altera Agilex5 SoCs. This reset is used by peripherals
> such as the SD/eMMC controller that share the combo PHY.
[...]

Applied to reset/fixes, thanks!

[1/9] dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5
      https://git.kernel.org/pub/scm/linux/kernel/git/pza/linux.git/commit/?id=ab45ecfab540

regards
Philipp

[PATCH v2 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

[Tanmay Kathpalia]

Extend the Cadence SDHCI binding to support the sixth-generation SD6HC
controller. Add the cdns,sd6hc compatible string with two named clocks
(ciu and biu) and three SD6HC-specific PHY timing properties for iocell
input/output delay and delay element size.

Add the altr,agilex5-sd6hc compatible string with three named reset
lines from the Altera HPS Reset Manager. Introduce per-variant
constraints so SD6HC and SD4HC each enforce their own clock, reset, and
PHY property requirements independently.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
---
 .../devicetree/bindings/mmc/cdns,sdhci.yaml   | 122 ++++++++++++++++--
 1 file changed, 111 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index 6c7317d13aa6..edd96e1d2bdc 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -4,21 +4,29 @@
 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
+title: Cadence SD/SDIO/eMMC Host Controller (SD4HC and SD6HC)
 
 maintainers:
   - Masahiro Yamada <yamada.masahiro@socionext.com>
+  - Tanmay Kathpalia <tanmay.kathpalia@altera.com>
 
 properties:
   compatible:
-    items:
-      - enum:
-          - amd,pensando-elba-sd4hc
-          - microchip,mpfs-sd4hc
-          - microchip,pic64gx-sd4hc
-          - mobileye,eyeq-sd4hc
-          - socionext,uniphier-sd4hc
-      - const: cdns,sd4hc
+    oneOf:
+      - description: Cadence SD4HC controller
+        items:
+          - enum:
+              - amd,pensando-elba-sd4hc
+              - microchip,mpfs-sd4hc
+              - microchip,pic64gx-sd4hc
+              - mobileye,eyeq-sd4hc
+              - socionext,uniphier-sd4hc
+          - const: cdns,sd4hc
+      - description: Cadence SD6HC controller
+        items:
+          - enum:
+              - altr,agilex5-sd6hc
+          - const: cdns,sd6hc
 
   reg:
     minItems: 1
@@ -28,10 +36,12 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   # PHY DLL input delays:
   # They are used to delay the data valid window, and align the window to
@@ -115,6 +125,25 @@ properties:
     minimum: 0
     maximum: 0x7f
 
+  # SD6HC PHY timing properties:
+  cdns,iocell-input-delay:
+    description: Input delay across IO cells in picoseconds
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 20000   # 20 ns
+
+  cdns,iocell-output-delay:
+    description: Output delay across IO cells in picoseconds
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 20000   # 20 ns
+
+  cdns,delay-element:
+    description: Delay element size in picoseconds
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 1000    # 1 ns
+
 required:
   - compatible
   - reg
@@ -139,6 +168,77 @@ allOf:
         reg:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: cdns,sd6hc
+    then:
+      description: SD6HC variant - use IO-cell and delay element properties
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: ciu
+            - const: biu
+        dma-coherent: true
+        iommus:
+          maxItems: 1
+        cdns,phy-input-delay-sd-highspeed: false
+        cdns,phy-input-delay-legacy: false
+        cdns,phy-input-delay-sd-uhs-sdr12: false
+        cdns,phy-input-delay-sd-uhs-sdr25: false
+        cdns,phy-input-delay-sd-uhs-sdr50: false
+        cdns,phy-input-delay-sd-uhs-ddr50: false
+        cdns,phy-input-delay-mmc-highspeed: false
+        cdns,phy-input-delay-mmc-ddr: false
+        cdns,phy-dll-delay-sdclk: false
+        cdns,phy-dll-delay-sdclk-hsmmc: false
+        cdns,phy-dll-delay-strobe: false
+      required:
+        - clock-names
+
+  # The Cadence SD6HC IP has per-clock-domain reset inputs, but the specific
+  # reset lines exposed here ("sdhc-reset", "combophy", "sdmmc-ocp") are
+  # provided by the Altera HPS Reset Manager and reflect the Agilex5 SoC
+  # integration.
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,agilex5-sd6hc
+    then:
+      properties:
+        resets:
+          minItems: 3
+          maxItems: 3
+        reset-names:
+          items:
+            - const: sdhc-reset
+            - const: combophy
+            - const: sdmmc-ocp
+      required:
+        - resets
+        - reset-names
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: cdns,sd4hc
+    then:
+      description: SD4HC variant - use legacy DLL delay properties
+      properties:
+        clocks:
+          maxItems: 1
+        resets:
+          maxItems: 1
+        cdns,iocell-input-delay: false
+        cdns,iocell-output-delay: false
+        cdns,delay-element: false
+
 unevaluatedProperties: false
 
 examples:
-- 
2.43.7

Re: [PATCH v2 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device tree schema guideline violation: standard properties are defined solely within conditional blocks.
--

commit e277493647bd6915b90ee32b253e1cb7514a8c5f
Author: Tanmay Kathpalia <tanmay.kathpalia@altera.com>

dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

Extend the Cadence SDHCI binding to support the sixth-generation SD6HC
controller. Add the cdns,sd6hc and altr,agilex5-sd6hc compatible strings
along with variant constraints.

> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 6c7317d13aa6c..edd96e1d2bdcd 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

[ ... ]

> @@ -139,6 +168,77 @@ allOf:
>          reg:
>            maxItems: 1
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: cdns,sd6hc
> +    then:
> +      description: SD6HC variant - use IO-cell and delay element properties
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +        clock-names:
> +          items:
> +            - const: ciu
> +            - const: biu
> +        dma-coherent: true
> +        iommus:
> +          maxItems: 1

[Severity: Low]
This isn't a bug, but should clock-names, dma-coherent, and iommus be
declared in the top-level properties block instead of solely within this
conditional?

The dt-schema guidelines suggest defining properties with their broadest
constraints at the top level rather than entirely within if:then blocks, to
ensure proper documentation generation and tooling compatibility.

[ ... ]

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: altr,agilex5-sd6hc
> +    then:
> +      properties:
> +        resets:
> +          minItems: 3
> +          maxItems: 3
> +        reset-names:
> +          items:
> +            - const: sdhc-reset
> +            - const: combophy
> +            - const: sdmmc-ocp

[Severity: Low]
Similar to the clock-names property, should reset-names also be declared at
the top level rather than being exclusively defined in this conditional block?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260627201457.12318-1-tanmay.kathpalia@altera.com?part=2

Re: [PATCH v2 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

[Kathpalia, Tanmay]

On 6/28/2026 1:56 AM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] Device tree schema guideline violation: standard properties are defined solely within conditional blocks.
> --
>
> commit e277493647bd6915b90ee32b253e1cb7514a8c5f
> Author: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>
> dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties
>
> Extend the Cadence SDHCI binding to support the sixth-generation SD6HC
> controller. Add the cdns,sd6hc and altr,agilex5-sd6hc compatible strings
> along with variant constraints.
>
>> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
>> index 6c7317d13aa6c..edd96e1d2bdcd 100644
>> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
>> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> [ ... ]
>
>> @@ -139,6 +168,77 @@ allOf:
>>           reg:
>>             maxItems: 1
>>   
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: cdns,sd6hc
>> +    then:
>> +      description: SD6HC variant - use IO-cell and delay element properties
>> +      properties:
>> +        clocks:
>> +          minItems: 2
>> +          maxItems: 2
>> +        clock-names:
>> +          items:
>> +            - const: ciu
>> +            - const: biu
>> +        dma-coherent: true
>> +        iommus:
>> +          maxItems: 1
> [Severity: Low]
> This isn't a bug, but should clock-names, dma-coherent, and iommus be
> declared in the top-level properties block instead of solely within this
> conditional?
>
> The dt-schema guidelines suggest defining properties with their broadest
> constraints at the top level rather than entirely within if:then blocks, to
> ensure proper documentation generation and tooling compatibility.

These properties are intentionally declared only within the if:/then:
block because they are exclusively valid for cdns,sd6hc hardware,
they are not applicable to cdns,sd4hc or other variants.

>
> [ ... ]
>
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: altr,agilex5-sd6hc
>> +    then:
>> +      properties:
>> +        resets:
>> +          minItems: 3
>> +          maxItems: 3
>> +        reset-names:
>> +          items:
>> +            - const: sdhc-reset
>> +            - const: combophy
>> +            - const: sdmmc-ocp
> [Severity: Low]
> Similar to the clock-names property, should reset-names also be declared at
> the top level rather than being exclusively defined in this conditional block?
Same reasoning as above - the three reset names (sdhc-reset,
combophy, sdmmc-ocp) are specific to the altr,agilex5-sd6hc
integration.

Re: [PATCH v2 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

[Krzysztof Kozlowski]

On Sat, Jun 27, 2026 at 01:14:47PM -0700, Tanmay Kathpalia wrote:
> Extend the Cadence SDHCI binding to support the sixth-generation SD6HC
> controller. Add the cdns,sd6hc compatible string with two named clocks
> (ciu and biu) and three SD6HC-specific PHY timing properties for iocell
> input/output delay and delay element size.
> 
> Add the altr,agilex5-sd6hc compatible string with three named reset
> lines from the Altera HPS Reset Manager. Introduce per-variant
> constraints so SD6HC and SD4HC each enforce their own clock, reset, and
> PHY property requirements independently.

You just repeated the diff. Instead describe the hardware.

> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
> ---
>  .../devicetree/bindings/mmc/cdns,sdhci.yaml   | 122 ++++++++++++++++--
>  1 file changed, 111 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 6c7317d13aa6..edd96e1d2bdc 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -4,21 +4,29 @@
>  $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
> +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC and SD6HC)
>  
>  maintainers:
>    - Masahiro Yamada <yamada.masahiro@socionext.com>
> +  - Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - amd,pensando-elba-sd4hc
> -          - microchip,mpfs-sd4hc
> -          - microchip,pic64gx-sd4hc
> -          - mobileye,eyeq-sd4hc
> -          - socionext,uniphier-sd4hc
> -      - const: cdns,sd4hc
> +    oneOf:
> +      - description: Cadence SD4HC controller

Drop description, you repeat the fallback compatible, so this is obvious.

> +        items:
> +          - enum:
> +              - amd,pensando-elba-sd4hc
> +              - microchip,mpfs-sd4hc
> +              - microchip,pic64gx-sd4hc
> +              - mobileye,eyeq-sd4hc
> +              - socionext,uniphier-sd4hc
> +          - const: cdns,sd4hc
> +      - description: Cadence SD6HC controller

Same here

> +        items:
> +          - enum:
> +              - altr,agilex5-sd6hc
> +          - const: cdns,sd6hc
>  
>    reg:
>      minItems: 1
> @@ -28,10 +36,12 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 3
>  
>    # PHY DLL input delays:
>    # They are used to delay the data valid window, and align the window to
> @@ -115,6 +125,25 @@ properties:
>      minimum: 0
>      maximum: 0x7f
>  
> +  # SD6HC PHY timing properties:
> +  cdns,iocell-input-delay:

Use standard unit suffixes from dtschema. I am pretty sure we have
picoseconds.

> +    description: Input delay across IO cells in picoseconds
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 20000   # 20 ns
> +
> +  cdns,iocell-output-delay:
> +    description: Output delay across IO cells in picoseconds
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 20000   # 20 ns
> +
> +  cdns,delay-element:
> +    description: Delay element size in picoseconds

None of these are deducible from the compatible? IOW, they differ in
each board with the same SoC?

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 1
> +    maximum: 1000    # 1 ns
> +
>  required:
>    - compatible
>    - reg
> @@ -139,6 +168,77 @@ allOf:
>          reg:
>            maxItems: 1
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: cdns,sd6hc
> +    then:
> +      description: SD6HC variant - use IO-cell and delay element properties
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +        clock-names:
> +          items:
> +            - const: ciu
> +            - const: biu

There is no property like clock-names. Look at the schema/binding.

> +        dma-coherent: true
> +        iommus:
> +          maxItems: 1a

Do not define properties in conditional block, but top level.

> +        cdns,phy-input-delay-sd-highspeed: false
> +        cdns,phy-input-delay-legacy: false
> +        cdns,phy-input-delay-sd-uhs-sdr12: false
> +        cdns,phy-input-delay-sd-uhs-sdr25: false
> +        cdns,phy-input-delay-sd-uhs-sdr50: false
> +        cdns,phy-input-delay-sd-uhs-ddr50: false
> +        cdns,phy-input-delay-mmc-highspeed: false
> +        cdns,phy-input-delay-mmc-ddr: false
> +        cdns,phy-dll-delay-sdclk: false
> +        cdns,phy-dll-delay-sdclk-hsmmc: false
> +        cdns,phy-dll-delay-strobe: false
> +      required:
> +        - clock-names

All this clearly suggests you should have own binding file.

Best regards,
Krzysztof

Re: [PATCH v2 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties

[Kathpalia, Tanmay]

Hi Krzysztof,

Thanks for the review.

On 6/29/2026 12:34 PM, Krzysztof Kozlowski wrote:
> On Sat, Jun 27, 2026 at 01:14:47PM -0700, Tanmay Kathpalia wrote:
>> Extend the Cadence SDHCI binding to support the sixth-generation SD6HC
>> controller. Add the cdns,sd6hc compatible string with two named clocks
>> (ciu and biu) and three SD6HC-specific PHY timing properties for iocell
>> input/output delay and delay element size.
>>
>> Add the altr,agilex5-sd6hc compatible string with three named reset
>> lines from the Altera HPS Reset Manager. Introduce per-variant
>> constraints so SD6HC and SD4HC each enforce their own clock, reset, and
>> PHY property requirements independently.
> You just repeated the diff. Instead describe the hardware.

Ack, I'll update the commit message to describe the SD6HC hardware
instead of summarizing the changes.
>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>>   .../devicetree/bindings/mmc/cdns,sdhci.yaml   | 122 ++++++++++++++++--
>>   1 file changed, 111 insertions(+), 11 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
>> index 6c7317d13aa6..edd96e1d2bdc 100644
>> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
>> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
>> @@ -4,21 +4,29 @@
>>   $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
>>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>>   
>> -title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
>> +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC and SD6HC)
>>   
>>   maintainers:
>>     - Masahiro Yamada <yamada.masahiro@socionext.com>
>> +  - Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>>   
>>   properties:
>>     compatible:
>> -    items:
>> -      - enum:
>> -          - amd,pensando-elba-sd4hc
>> -          - microchip,mpfs-sd4hc
>> -          - microchip,pic64gx-sd4hc
>> -          - mobileye,eyeq-sd4hc
>> -          - socionext,uniphier-sd4hc
>> -      - const: cdns,sd4hc
>> +    oneOf:
>> +      - description: Cadence SD4HC controller
> Drop description, you repeat the fallback compatible, so this is obvious.

I'll remove the redundant descriptions.
>
>> +        items:
>> +          - enum:
>> +              - amd,pensando-elba-sd4hc
>> +              - microchip,mpfs-sd4hc
>> +              - microchip,pic64gx-sd4hc
>> +              - mobileye,eyeq-sd4hc
>> +              - socionext,uniphier-sd4hc
>> +          - const: cdns,sd4hc
>> +      - description: Cadence SD6HC controller
> Same here

Ack.

>
>> +        items:
>> +          - enum:
>> +              - altr,agilex5-sd6hc
>> +          - const: cdns,sd6hc
>>   
>>     reg:
>>       minItems: 1
>> @@ -28,10 +36,12 @@ properties:
>>       maxItems: 1
>>   
>>     clocks:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 2
>>   
>>     resets:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 3
>>   
>>     # PHY DLL input delays:
>>     # They are used to delay the data valid window, and align the window to
>> @@ -115,6 +125,25 @@ properties:
>>       minimum: 0
>>       maximum: 0x7f
>>   
>> +  # SD6HC PHY timing properties:
>> +  cdns,iocell-input-delay:
> Use standard unit suffixes from dtschema. I am pretty sure we have
> picoseconds.

I'll rename these properties to use the standard dtschema unit
suffixes.

>
>> +    description: Input delay across IO cells in picoseconds
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    minimum: 0
>> +    maximum: 20000   # 20 ns
>> +
>> +  cdns,iocell-output-delay:
>> +    description: Output delay across IO cells in picoseconds
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    minimum: 0
>> +    maximum: 20000   # 20 ns
>> +
>> +  cdns,delay-element:
>> +    description: Delay element size in picoseconds
> None of these are deducible from the compatible? IOW, they differ in
> each board with the same SoC?

These values are board/platform dependent and are provided by
the platform integration rather than being fixed by the controller
compatible.

>
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    minimum: 1
>> +    maximum: 1000    # 1 ns
>> +
>>   required:
>>     - compatible
>>     - reg
>> @@ -139,6 +168,77 @@ allOf:
>>           reg:
>>             maxItems: 1
>>   
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: cdns,sd6hc
>> +    then:
>> +      description: SD6HC variant - use IO-cell and delay element properties
>> +      properties:
>> +        clocks:
>> +          minItems: 2
>> +          maxItems: 2
>> +        clock-names:
>> +          items:
>> +            - const: ciu
>> +            - const: biu
> There is no property like clock-names. Look at the schema/binding.

Ack, I'll fix this.

>
>> +        dma-coherent: true
>> +        iommus:
>> +          maxItems: 1a
> Do not define properties in conditional block, but top level.

I'll move them to the top level as suggested.

>
>> +        cdns,phy-input-delay-sd-highspeed: false
>> +        cdns,phy-input-delay-legacy: false
>> +        cdns,phy-input-delay-sd-uhs-sdr12: false
>> +        cdns,phy-input-delay-sd-uhs-sdr25: false
>> +        cdns,phy-input-delay-sd-uhs-sdr50: false
>> +        cdns,phy-input-delay-sd-uhs-ddr50: false
>> +        cdns,phy-input-delay-mmc-highspeed: false
>> +        cdns,phy-input-delay-mmc-ddr: false
>> +        cdns,phy-dll-delay-sdclk: false
>> +        cdns,phy-dll-delay-sdclk-hsmmc: false
>> +        cdns,phy-dll-delay-strobe: false
>> +      required:
>> +        - clock-names
> All this clearly suggests you should have own binding file.

Agreed. I'll split the SD6HC support into a separate binding
file and address the above comments in v3.

>

[PATCH v2 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

[Tanmay Kathpalia]

Add the Cadence SD6HC controller node to the Agilex5 SoC DTSI as a
shared SD/eMMC node, disabled by default. The controller integrates
with the system SMMU for IOMMU support and uses SDMCLK as the primary
clock source for PHY timing.

On the SOCDK board, add a fixed 3.3V regulator for card power and a
GPIO-controlled regulator for I/O voltage switching between 1.8V and
3.3V. Enable the controller for SD-only operation in 4-bit bus width
with high-speed and SDR104 UHS-I modes at 200 MHz.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 25 +++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 31 +++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 02e62d954e94..f552aa0c1faa 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -300,6 +300,31 @@ portb: gpio-controller@0 {
 			};
 		};
 
+		/*
+		 * Shared SD/eMMC controller node. On the SOCDK OOBE daughter-card
+		 * this is used for SD card operation; on the SOCDK eMMC daughter-card
+		 * it is configured for eMMC.
+		 */
+		emmc: mmc@10808000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
+			reg = <0x10808000 0x1000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>;
+			reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
+			/*
+			 * "ciu" (SDMCLK) is listed first so it is selected as the
+			 * primary clock by the SDHCI platform layer; the SD6HC PHY
+			 * timing calculations are derived from this clock rate.
+			 */
+			clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>;
+			clock-names = "ciu", "biu";
+			iommus = <&smmu 5>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		nand: nand-controller@10b80000 {
 			compatible = "cdns,hp-nfc";
 			reg = <0x10b80000 0x10000>,
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..c56f46721bb0 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -34,6 +34,24 @@ memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
+
+	vmmc_reg: regulator-fixed-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vqmmc_io_reg: regulator-1p8v {
+		compatible = "regulator-gpio";
+		regulator-name = "vqmmc-io";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		states =	<1800000 0x1>,
+				<3300000 0x0>;
+		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 &gpio0 {
@@ -98,6 +116,19 @@ root: partition@4200000 {
 	};
 };
 
+&emmc {
+	status = "okay";
+
+	no-mmc;
+	disable-wp;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vmmc_reg>;
+	vqmmc-supply = <&vqmmc_io_reg>;
+	max-frequency = <200000000>;
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.43.7

Re: [PATCH v2 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The GPIO-controlled I/O regulator (vqmmc-io) initializes to 1.8V instead of the required 3.3V at boot due to missing `gpios-states` property.
--

commit d6ddf71779dce5e00733c866f08e72b6d91c3a47
Author: Tanmay Kathpalia <tanmay.kathpalia@altera.com>

arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

This commit adds the Cadence SD6HC controller node to the Agilex5 SoC DTSI
and enables it for the SOCDK board. It configures the controller for SD-only
operation with a fixed 3.3V card power regulator and a GPIO-controlled I/O
voltage regulator.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index 262bb3e8e5c72..c56f46721bb06 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

[ ... ]

> @@ -34,6 +34,24 @@ memory@80000000 {
>  		/* We expect the bootloader to fill in the reg */
>  		reg = <0x0 0x80000000 0x0 0x0>;
>  	};
> +
> +	vmmc_reg: regulator-fixed-3p3v {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc-sd";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
> +	vqmmc_io_reg: regulator-1p8v {
> +		compatible = "regulator-gpio";
> +		regulator-name = "vqmmc-io";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		states =	<1800000 0x1>,
> +				<3300000 0x0>;
> +		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
> +	};

[Severity: High]
Does this missing gpios-states property cause the regulator to initialize
incorrectly at boot?

In drivers/regulator/gpio-regulator.c, when gpios-states is omitted,
of_get_gpio_regulator_config() defaults the GPIO to GPIOD_OUT_HIGH. Based
on the states array here, a high state (0x1) selects 1.8V instead of the
standard 3.3V required for initial SD card operation.

Could this violate SD card power sequencing by supplying 1.8V to the I/O
lines while VDD is 3.3V, potentially causing enumeration failures or
electrical damage?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260627201457.12318-1-tanmay.kathpalia@altera.com?part=3

Re: [PATCH v2 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

[Kathpalia, Tanmay]

On 6/28/2026 1:54 AM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] The GPIO-controlled I/O regulator (vqmmc-io) initializes to 1.8V instead of the required 3.3V at boot due to missing `gpios-states` property.
> --
>
> commit d6ddf71779dce5e00733c866f08e72b6d91c3a47
> Author: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>
> arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement
>
> This commit adds the Cadence SD6HC controller node to the Agilex5 SoC DTSI
> and enables it for the SOCDK board. It configures the controller for SD-only
> operation with a fixed 3.3V card power regulator and a GPIO-controlled I/O
> voltage regulator.
>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
>> index 262bb3e8e5c72..c56f46721bb06 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> [ ... ]
>
>> @@ -34,6 +34,24 @@ memory@80000000 {
>>   		/* We expect the bootloader to fill in the reg */
>>   		reg = <0x0 0x80000000 0x0 0x0>;
>>   	};
>> +
>> +	vmmc_reg: regulator-fixed-3p3v {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vcc-sd";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		regulator-always-on;
>> +	};
>> +
>> +	vqmmc_io_reg: regulator-1p8v {
>> +		compatible = "regulator-gpio";
>> +		regulator-name = "vqmmc-io";
>> +		regulator-min-microvolt = <1800000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		states =	<1800000 0x1>,
>> +				<3300000 0x0>;
>> +		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
>> +	};
> [Severity: High]
> Does this missing gpios-states property cause the regulator to initialize
> incorrectly at boot?
>
> In drivers/regulator/gpio-regulator.c, when gpios-states is omitted,
> of_get_gpio_regulator_config() defaults the GPIO to GPIOD_OUT_HIGH. Based
> on the states array here, a high state (0x1) selects 1.8V instead of the
> standard 3.3V required for initial SD card operation.
>
> Could this violate SD card power sequencing by supplying 1.8V to the I/O
> lines while VDD is 3.3V, potentially causing enumeration failures or
> electrical damage?

Correct. Will add gpios-states = <0>; to initialize at 3.3V and fold it into
v3 with any other feedback.

Re: [PATCH v2 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

[Krzysztof Kozlowski]

On Sat, Jun 27, 2026 at 01:14:48PM -0700, Tanmay Kathpalia wrote:
> Add the Cadence SD6HC controller node to the Agilex5 SoC DTSI as a
> shared SD/eMMC node, disabled by default. The controller integrates
> with the system SMMU for IOMMU support and uses SDMCLK as the primary
> clock source for PHY timing.
> 
> On the SOCDK board, add a fixed 3.3V regulator for card power and a
> GPIO-controlled regulator for I/O voltage switching between 1.8V and
> 3.3V. Enable the controller for SD-only operation in 4-bit bus width
> with high-speed and SDR104 UHS-I modes at 200 MHz.
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 25 +++++++++++++++
>  .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 31 +++++++++++++++++++
>  2 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 02e62d954e94..f552aa0c1faa 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -300,6 +300,31 @@ portb: gpio-controller@0 {
>  			};
>  		};
>  
> +		/*
> +		 * Shared SD/eMMC controller node. On the SOCDK OOBE daughter-card
> +		 * this is used for SD card operation; on the SOCDK eMMC daughter-card
> +		 * it is configured for eMMC.
> +		 */
> +		emmc: mmc@10808000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;

Please follow DTS coding style for new code.

> +			compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
> +			reg = <0x10808000 0x1000>;
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>;
> +			reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
> +			/*
> +			 * "ciu" (SDMCLK) is listed first so it is selected as the
> +			 * primary clock by the SDHCI platform layer; the SD6HC PHY
> +			 * timing calculations are derived from this clock rate.
> +			 */
> +			clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>;
> +			clock-names = "ciu", "biu";
> +			iommus = <&smmu 5>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +
>  		nand: nand-controller@10b80000 {
>  			compatible = "cdns,hp-nfc";
>  			reg = <0x10b80000 0x10000>,
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index 262bb3e8e5c7..c56f46721bb0 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> @@ -34,6 +34,24 @@ memory@80000000 {
>  		/* We expect the bootloader to fill in the reg */
>  		reg = <0x0 0x80000000 0x0 0x0>;
>  	};
> +
> +	vmmc_reg: regulator-fixed-3p3v {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc-sd";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
> +	vqmmc_io_reg: regulator-1p8v {
> +		compatible = "regulator-gpio";
> +		regulator-name = "vqmmc-io";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		states =	<1800000 0x1>,

There is only one space after '='.

> +				<3300000 0x0>;
> +		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
> +	};
>  };

Best regards,
Krzysztof

Re: [PATCH v2 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

[Kathpalia, Tanmay]

Hi Krzysztof,

Thanks for the review.

On 6/29/2026 12:36 PM, Krzysztof Kozlowski wrote:
> On Sat, Jun 27, 2026 at 01:14:48PM -0700, Tanmay Kathpalia wrote:
>> Add the Cadence SD6HC controller node to the Agilex5 SoC DTSI as a
>> shared SD/eMMC node, disabled by default. The controller integrates
>> with the system SMMU for IOMMU support and uses SDMCLK as the primary
>> clock source for PHY timing.
>>
>> On the SOCDK board, add a fixed 3.3V regulator for card power and a
>> GPIO-controlled regulator for I/O voltage switching between 1.8V and
>> 3.3V. Enable the controller for SD-only operation in 4-bit bus width
>> with high-speed and SDR104 UHS-I modes at 200 MHz.
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 25 +++++++++++++++
>>   .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 31 +++++++++++++++++++
>>   2 files changed, 56 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index 02e62d954e94..f552aa0c1faa 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -300,6 +300,31 @@ portb: gpio-controller@0 {
>>   			};
>>   		};
>>   
>> +		/*
>> +		 * Shared SD/eMMC controller node. On the SOCDK OOBE daughter-card
>> +		 * this is used for SD card operation; on the SOCDK eMMC daughter-card
>> +		 * it is configured for eMMC.
>> +		 */
>> +		emmc: mmc@10808000 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
> Please follow DTS coding style for new code.

Ack, I'll update the DTS formatting to follow the coding style in v3.

>
>> +			compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
>> +			reg = <0x10808000 0x1000>;
>> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +			resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>;
>> +			reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
>> +			/*
>> +			 * "ciu" (SDMCLK) is listed first so it is selected as the
>> +			 * primary clock by the SDHCI platform layer; the SD6HC PHY
>> +			 * timing calculations are derived from this clock rate.
>> +			 */
>> +			clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>;
>> +			clock-names = "ciu", "biu";
>> +			iommus = <&smmu 5>;
>> +			dma-coherent;
>> +			status = "disabled";
>> +		};
>> +
>>   		nand: nand-controller@10b80000 {
>>   			compatible = "cdns,hp-nfc";
>>   			reg = <0x10b80000 0x10000>,
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
>> index 262bb3e8e5c7..c56f46721bb0 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
>> @@ -34,6 +34,24 @@ memory@80000000 {
>>   		/* We expect the bootloader to fill in the reg */
>>   		reg = <0x0 0x80000000 0x0 0x0>;
>>   	};
>> +
>> +	vmmc_reg: regulator-fixed-3p3v {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vcc-sd";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		regulator-always-on;
>> +	};
>> +
>> +	vqmmc_io_reg: regulator-1p8v {
>> +		compatible = "regulator-gpio";
>> +		regulator-name = "vqmmc-io";
>> +		regulator-min-microvolt = <1800000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		states =	<1800000 0x1>,
> There is only one space after '='.

I'll fix the formatting in v3.

>
>> +				<3300000 0x0>;
>> +		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
>> +	};
>>   };
> Best regards,
> Krzysztof
>

[PATCH v2 4/9] dt-bindings: arm: intel: add Agilex5 SOCDK eMMC board variant

[Tanmay Kathpalia]

Add "intel,socfpga-agilex5-socdk-emmc" compatible string for the
Agilex5 SOCDK board variant configured with eMMC storage.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
---
 Documentation/devicetree/bindings/arm/altera.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 206686f3eebc..f5efcbc381b8 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -113,6 +113,7 @@ properties:
               - intel,socfpga-agilex5-socdk-013b
               - intel,socfpga-agilex5-socdk-modular
               - intel,socfpga-agilex5-socdk-nand
+              - intel,socfpga-agilex5-socdk-emmc
           - const: intel,socfpga-agilex5
 
       - description: SoCFPGA VT
-- 
2.43.7

Re: [PATCH v2 4/9] dt-bindings: arm: intel: add Agilex5 SOCDK eMMC board variant

[Krzysztof Kozlowski]

On Sat, Jun 27, 2026 at 01:14:49PM -0700, Tanmay Kathpalia wrote:
> Add "intel,socfpga-agilex5-socdk-emmc" compatible string for the
> Agilex5 SOCDK board variant configured with eMMC storage.
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
> ---
>  Documentation/devicetree/bindings/arm/altera.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
> index 206686f3eebc..f5efcbc381b8 100644
> --- a/Documentation/devicetree/bindings/arm/altera.yaml
> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
> @@ -113,6 +113,7 @@ properties:
>                - intel,socfpga-agilex5-socdk-013b
>                - intel,socfpga-agilex5-socdk-modular
>                - intel,socfpga-agilex5-socdk-nand
> +              - intel,socfpga-agilex5-socdk-emmc

Do not break the order of entries.

Best regards,
Krzysztof

Re: [PATCH v2 4/9] dt-bindings: arm: intel: add Agilex5 SOCDK eMMC board variant

[Kathpalia, Tanmay]

On 6/29/2026 12:36 PM, Krzysztof Kozlowski wrote:
> On Sat, Jun 27, 2026 at 01:14:49PM -0700, Tanmay Kathpalia wrote:
>> Add "intel,socfpga-agilex5-socdk-emmc" compatible string for the
>> Agilex5 SOCDK board variant configured with eMMC storage.
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>>   Documentation/devicetree/bindings/arm/altera.yaml | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
>> index 206686f3eebc..f5efcbc381b8 100644
>> --- a/Documentation/devicetree/bindings/arm/altera.yaml
>> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>> @@ -113,6 +113,7 @@ properties:
>>                 - intel,socfpga-agilex5-socdk-013b
>>                 - intel,socfpga-agilex5-socdk-modular
>>                 - intel,socfpga-agilex5-socdk-nand
>> +              - intel,socfpga-agilex5-socdk-emmc
> Do not break the order of entries.

Ack.
>
>

[PATCH v2 5/9] arm64: dts: agilex5: add SOCDK eMMC daughter board support

[Tanmay Kathpalia]

Add socfpga_agilex5_socdk_emmc.dts for the Agilex5 SoCDK eMMC daughter
board variant. Define board-specific regulators at the DTS root: a
fixed 3.3V supply for card power and a fixed 1.8V supply for eMMC I/O
voltage.

Enable the shared SD/eMMC controller for eMMC-only operation with an
8-bit bus, HS200 and HS400 modes at 1.8V signaling, and a 200 MHz
maximum clock frequency.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
---
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../dts/intel/socfpga_agilex5_socdk_emmc.dts  | 120 ++++++++++++++++++
 2 files changed, 121 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 33fcc55d0cb9..5bbbcfda1f48 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex5_socdk_013b.dtb \
 				socfpga_agilex5_socdk_modular.dtb \
 				socfpga_agilex5_socdk_nand.dtb \
+				socfpga_agilex5_socdk_emmc.dtb \
 				socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
new file mode 100644
index 000000000000..455808db32bb
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex5 SoCDK eMMC daughter board";
+	compatible = "intel,socfpga-agilex5-socdk-emmc", "intel,socfpga-agilex5";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "hps_led0";
+			gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			label = "hps_led1";
+			gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	vmmc_reg: regulator-fixed-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-emmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vqmmc_io_reg: regulator-fixed-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "vqmmc-io";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&emac0_phy0>;
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		emac0_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i3c0 {
+	status = "okay";
+};
+
+&i3c1 {
+	status = "okay";
+};
+
+&emmc {
+	status = "okay";
+
+	no-sd;
+	no-sdio;
+	disable-wp;
+	non-removable;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	bus-width = <8>;
+	vmmc-supply = <&vmmc_reg>;
+	vqmmc-supply = <&vqmmc_io_reg>;
+	max-frequency = <200000000>;
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
-- 
2.43.7

Re: [PATCH v2 5/9] arm64: dts: agilex5: add SOCDK eMMC daughter board support

[Krzysztof Kozlowski]

On Sat, Jun 27, 2026 at 01:14:50PM -0700, Tanmay Kathpalia wrote:
> Add socfpga_agilex5_socdk_emmc.dts for the Agilex5 SoCDK eMMC daughter
> board variant. Define board-specific regulators at the DTS root: a
> fixed 3.3V supply for card power and a fixed 1.8V supply for eMMC I/O
> voltage.
> 
> Enable the shared SD/eMMC controller for eMMC-only operation with an
> 8-bit bus, HS200 and HS400 modes at 1.8V signaling, and a 200 MHz
> maximum clock frequency.
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
> ---
>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>  .../dts/intel/socfpga_agilex5_socdk_emmc.dts  | 120 ++++++++++++++++++
>  2 files changed, 121 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
> 
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index 33fcc55d0cb9..5bbbcfda1f48 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>  				socfpga_agilex5_socdk_013b.dtb \
>  				socfpga_agilex5_socdk_modular.dtb \
>  				socfpga_agilex5_socdk_nand.dtb \
> +				socfpga_agilex5_socdk_emmc.dtb \

Same mistakes... Do not introduce random order.

Best regards,
Krzysztof

Re: [PATCH v2 5/9] arm64: dts: agilex5: add SOCDK eMMC daughter board support

[Kathpalia, Tanmay]

On 6/29/2026 12:37 PM, Krzysztof Kozlowski wrote:
> On Sat, Jun 27, 2026 at 01:14:50PM -0700, Tanmay Kathpalia wrote:
>> Add socfpga_agilex5_socdk_emmc.dts for the Agilex5 SoCDK eMMC daughter
>> board variant. Define board-specific regulators at the DTS root: a
>> fixed 3.3V supply for card power and a fixed 1.8V supply for eMMC I/O
>> voltage.
>>
>> Enable the shared SD/eMMC controller for eMMC-only operation with an
>> 8-bit bus, HS200 and HS400 modes at 1.8V signaling, and a 200 MHz
>> maximum clock frequency.
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>>   arch/arm64/boot/dts/intel/Makefile            |   1 +
>>   .../dts/intel/socfpga_agilex5_socdk_emmc.dts  | 120 ++++++++++++++++++
>>   2 files changed, 121 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
>> index 33fcc55d0cb9..5bbbcfda1f48 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>>   				socfpga_agilex5_socdk_013b.dtb \
>>   				socfpga_agilex5_socdk_modular.dtb \
>>   				socfpga_agilex5_socdk_nand.dtb \
>> +				socfpga_agilex5_socdk_emmc.dtb \
> Same mistakes... Do not introduce random order.

Ack.

>
>