Re: [PATCHv2 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch adds 16 additional queue interrupts to the gmac1 and gmac2 device tree nodes, violating the strict `maxItems: 1` constraint in the `altr,socfpga-stmmac.yaml` binding schema.
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commit 40c2d176bae16fd4cc692701cf60a99607edf61f
Author: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs
in the agilex5 device tree.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 02e62d954e949..140e4bf9fb155 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
>  			compatible = "altr,socfpga-stmmac-agilex5",
>  				     "snps,dwxgmac-2.10";
>  			reg = <0x10820000 0x3500>;
> -			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "macirq";
> +			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
Does this expansion of the interrupts list trigger a dtbs_check warning?

Looking at Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml,
it strictly limits interrupts:

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: macirq

Should the binding schema be updated concurrently with the dtsi to allow these
queue-specific interrupts and avoid validation failures?

[ ... ]

> @@ -783,8 +815,40 @@ gmac2: ethernet@10830000 {
>  			compatible = "altr,socfpga-stmmac-agilex5",
>  				     "snps,dwxgmac-2.10";
>  			reg = <0x10830000 0x3500>;
> -			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "macirq";
> +			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,

[Severity: Low]
Same question here regarding the altr,socfpga-stmmac.yaml binding schema
limiting interrupts to maxItems: 1.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260629114818.1746410-2-dinguyen@kernel.org?part=1