[PATCH 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs

[PATCH 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs

[Ioana Ciornei]

This patch set adds the device tree nodes for the Lynx10G SerDes blocks
found on the LS1028A, LS1046A, LS1088A and LS2088A SoCs.

The first patch also transitions the LX2160A SoC dtsi to use the
device-specific Lynx28G SerDes compatible.

Ioana Ciornei (1):
  arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks

Vladimir Oltean (4):
  arm64: dts: lx2160a: transition to device-specific SerDes compatible
    strings
  arm64: dts: ls1028a: describe the Lynx 10G SerDes
  arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
  arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks

 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  29 ++++
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  60 +++++++
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  58 +++++++
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  98 ++++++++++++
 .../freescale/fsl-lx2160a-clearfog-itx.dtsi   |   4 +
 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |   4 +
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
 .../dts/freescale/fsl-lx2162a-clearfog.dts    |   2 +-
 .../boot/dts/freescale/fsl-lx2162a-qds.dts    |   2 +-
 .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi |  24 +++
 10 files changed, 427 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi

-- 
2.25.1

[PATCH 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings

[Ioana Ciornei]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
instance is present in the compatible string, to allow reliable per-lane
capability detection and per-lane customization of electrical properties.

These new bindings have #phy-cells = <0> in per-lane PHY providers, so
we need to update consumer phandles as well.

The modern bindings are backward-incompatible with old kernels, due
to the consumer phandles being either in one form or in another, as
explained here:
https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/

One of the major differences between the LX2160A and LX2162A is the
SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
split that up even further, and derive a fsl-lx2162a.dtsi which
overrides the SerDes properties.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 .../freescale/fsl-lx2160a-clearfog-itx.dtsi   |   4 +
 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |   4 +
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
 .../dts/freescale/fsl-lx2162a-clearfog.dts    |   2 +-
 .../boot/dts/freescale/fsl-lx2162a-qds.dts    |   2 +-
 .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi |  24 +++
 6 files changed, 182 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 4bc151d721dd..1f946d3a4ec0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -135,6 +135,10 @@ &sata3 {
 	status = "okay";
 };
 
+&serdes_1 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 935f421475ac..a40a968b9533 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -329,6 +329,10 @@ &uart0 {
 	status = "okay";
 };
 
+&serdes_1 {
+	status = "okay";
+};
+
 &uart1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 1d73abffa6b7..a687eb3e3190 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -621,17 +621,163 @@ soc: soc {
 		ranges;
 		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 
+		/* Note on the interpretation of SerDes lane numbering from
+		 * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
+		 * The letters (A-H) correspond to logical lane numbers in the
+		 * SerDes register map (lane A's registers start with LNAGCR0),
+		 * while the numbers (0-7) correspond to physical lanes as
+		 * routed to pins.  SerDes block #1 is flipped in the LX2160A
+		 * floorplan (logical lane A goes to physical lane 7's pins),
+		 * while SerDes blocks #2 and #3 are not.  The lanes below are
+		 * listed right to left when looking at that table.
+		 * Both the numbers and the letters are according to the logical
+		 * numbering scheme, and do not account for the flipping.
+		 */
 		serdes_1: phy@1ea0000 {
-			compatible = "fsl,lynx-28g";
+			compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
 			reg = <0x0 0x1ea0000 0x0 0x1e30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes_1_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_e: phy@4 {
+				reg = <4>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_f: phy@5 {
+				reg = <5>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_g: phy@6 {
+				reg = <6>;
+				#phy-cells = <0>;
+			};
+
+			serdes_1_lane_h: phy@7 {
+				reg = <7>;
+				#phy-cells = <0>;
+			};
 		};
 
 		serdes_2: phy@1eb0000 {
-			compatible = "fsl,lynx-28g";
+			compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g";
 			reg = <0x0 0x1eb0000 0x0 0x1e30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			#phy-cells = <1>;
 			status = "disabled";
+
+			serdes_2_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_e: phy@4 {
+				reg = <4>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_f: phy@5 {
+				reg = <5>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_g: phy@6 {
+				reg = <6>;
+				#phy-cells = <0>;
+			};
+
+			serdes_2_lane_h: phy@7 {
+				reg = <7>;
+				#phy-cells = <0>;
+			};
+		};
+
+		serdes_3: phy@1ec0000 {
+			compatible = "fsl,lx2160a-serdes3";
+			reg = <0x0 0x1ec0000 0x0 0x1e30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			#phy-cells = <1>;
+
+			serdes_3_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_e: phy@4 {
+				reg = <4>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_f: phy@5 {
+				reg = <5>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_g: phy@6 {
+				reg = <6>;
+				#phy-cells = <0>;
+			};
+
+			serdes_3_lane_h: phy@7 {
+				reg = <7>;
+				#phy-cells = <0>;
+			};
 		};
 
 		crypto: crypto@8000000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 99ee2b1c0f13..61e70e9c6e80 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -8,7 +8,7 @@
 
 #include <dt-bindings/leds/common.h>
 
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
 #include "fsl-lx2162a-sr-som.dtsi"
 
 / {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 7a595fddc027..0ba56b9819ac 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
 
 / {
 	model = "NXP Layerscape LX2162AQDS";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
new file mode 100644
index 000000000000..b9629e074d94
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2162A family SoC.
+//
+// Copyright 2025 NXP
+
+#include "fsl-lx2160a-rev2.dtsi"
+
+&serdes_1 {
+	compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
+
+	/delete-node/ phy@0;
+	/delete-node/ phy@1;
+	/delete-node/ phy@2;
+	/delete-node/ phy@3;
+};
+
+&serdes_2 {
+	compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
+};
+
+&soc {
+	/delete-node/ serdes@1ec0000;
+};
-- 
2.25.1

[PATCH 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes

[Ioana Ciornei]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the
LS1028A SoC. The node is left disabled at the SoC level; board DTs will
be expected to enable it once the consumer Ethernet nodes use it.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index f4ba3d16ab86..b4abdb5f906a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
 			};
 		};
 
+		serdes: phy@1ea0000 {
+			compatible = "fsl,ls1028a-serdes";
+			reg = <0x00 0x1ea0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+		};
+
 		scfg: syscon@1fc0000 {
 			compatible = "fsl,ls1028a-scfg", "syscon";
 			reg = <0x0 0x1fc0000 0x0 0x10000>;
-- 
2.25.1

[PATCH 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks

[Ioana Ciornei]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1046A SoC. The nodes are left disabled at the SoC level; board
DTs will be expected to enable them once the consumer Ethernet nodes
appear.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 6fefe837f434..db935805c379 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
 			clock-names = "sfp";
 		};
 
+		serdes1: phy@1ea0000 {
+			compatible = "fsl,ls1046a-serdes1";
+			reg = <0x00 0x1ea0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			big-endian;
+			status = "disabled";
+
+			serdes1_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+		};
+
+		serdes2: phy@1eb0000 {
+			compatible = "fsl,ls1046a-serdes2";
+			reg = <0x00 0x1eb0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			big-endian;
+			status = "disabled";
+
+			serdes2_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1046a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
-- 
2.25.1

[PATCH 4/5] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks

[Ioana Ciornei]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS208xA SoC. The nodes are left disabled at the SoC level; board
DTs will enabled them once there are consumers.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 6073e426774a..7d4260661766 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -280,6 +280,104 @@ sfp: efuse@1e80000 {
 			clock-names = "sfp";
 		};
 
+		serdes1: phy@1ea0000 {
+			compatible = "fsl,ls2088a-serdes1";
+			reg = <0x00 0x1ea0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes1_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_e: phy@4 {
+				reg = <4>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_f: phy@5 {
+				reg = <5>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_g: phy@6 {
+				reg = <6>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_h: phy@7 {
+				reg = <7>;
+				#phy-cells = <0>;
+			};
+		};
+
+		serdes2: phy@1eb0000 {
+			compatible = "fsl,ls2088a-serdes2";
+			reg = <0x00 0x1eb0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes2_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_e: phy@4 {
+				reg = <4>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_f: phy@5 {
+				reg = <5>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_g: phy@6 {
+				reg = <6>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_h: phy@7 {
+				reg = <7>;
+				#phy-cells = <0>;
+			};
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,ls2080a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
-- 
2.25.1

[PATCH 5/5] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks

[Ioana Ciornei]

Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1088A SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 99016768b73f..dcf13ac1fce5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -239,6 +239,64 @@ reset: syscon@1e60000 {
 			reg = <0x0 0x1e60000 0x0 0x10000>;
 		};
 
+		serdes1: phy@1ea0000 {
+			compatible = "fsl,ls1088a-serdes1";
+			reg = <0x00 0x1ea0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes1_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes1_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+		};
+
+		serdes2: phy@1eb0000 {
+			compatible = "fsl,ls1088a-serdes2";
+			reg = <0x00 0x1eb0000 0x0 0xffff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+
+			serdes2_lane_a: phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_b: phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_c: phy@2 {
+				reg = <2>;
+				#phy-cells = <0>;
+			};
+
+			serdes2_lane_d: phy@3 {
+				reg = <3>;
+				#phy-cells = <0>;
+			};
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,ls1088a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
-- 
2.25.1

Re: [PATCH 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Unintentional disabling of `serdes_1` on multiple boards.
- [Medium] Consumer phandles for SerDes PHYs were not updated to match the new per-lane PHY providers, contradicting the commit message.
- [Medium] The newly added `serdes_3` node is missing the generic fallback compatible string `fsl,lynx-28g`.
- [Low] Device tree compilation fails due to incorrect node name in `/delete-node/` directive for serdes_3.
--

commit dcf5b2d58e1afb24aa2ae2829db182c735a1dfc1
Author: Vladimir Oltean <vladimir.oltean@nxp.com>

arm64: dts: lx2160a: transition to device-specific SerDes compatible strings

Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
instance is present in the compatible string, to allow reliable per-lane
capability detection and per-lane customization of electrical properties.

>     These new bindings have #phy-cells = <0> in per-lane PHY providers, so
>     we need to update consumer phandles as well.

[Severity: Medium]
Did we miss updating the consumer phandles in this patch?

The commit message indicates consumer phandles need updating to match
#phy-cells = <0>, but they appear to remain unupdated in the device tree,
and #phy-cells = <1> is still retained on the parent PHY nodes.

> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 1d73abffa6b72..a687eb3e31904 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -621,17 +621,163 @@ soc: soc {
>  		ranges;
>  		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
>  
[ ... ]
>  		serdes_1: phy@1ea0000 {
> -			compatible = "fsl,lynx-28g";
> +			compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
>  			reg = <0x0 0x1ea0000 0x0 0x1e30>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
>  			#phy-cells = <1>;
> +			status = "disabled";

[Severity: High]
Does this default status = "disabled" unintentionally break interfaces
wired to serdes_1 on boards like fsl-lx2162a-clearfog and fsl-lx2160a-half-twins?

These boards consume serdes_1 but do not appear to override the status to
"okay" in this patch.

[ ... ]
> +		serdes_3: phy@1ec0000 {
> +			compatible = "fsl,lx2160a-serdes3";
> +			reg = <0x0 0x1ec0000 0x0 0x1e30>;

[Severity: Medium]
Should serdes_3 include the generic "fsl,lynx-28g" fallback compatible string
here, similar to what was added for serdes_1 and serdes_2?

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +			#phy-cells = <1>;
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> new file mode 100644
> index 0000000000000..b9629e074d943
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> @@ -0,0 +1,24 @@
[ ... ]
> +&soc {
> +	/delete-node/ serdes@1ec0000;
> +};

[Severity: Low]
Could this /delete-node/ directive fail at build time?

In the base fsl-lx2160a.dtsi, the node is defined as phy@1ec0000 rather
than serdes@1ec0000.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630110459.516364-1-ioana.ciornei@nxp.com?part=1

Re: [PATCH 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `reg` property for the `serdes` node incorrectly sets the region size to `0xffff` instead of `0x10000`, causing an off-by-one error in the resource length.
--

commit a39aeb25ec050b4deb66ed84479cc1400f6ce47b
Author: Vladimir Oltean <vladimir.oltean@nxp.com>

arm64: dts: ls1028a: describe the Lynx 10G SerDes

This commit describes the Lynx 10G SerDes block and its 4 SerDes lanes found
on the LS1028A SoC. The node is left disabled at the SoC level so board
device trees can enable it once consumer nodes use it.

> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
[ ... ]
> @@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
>  			};
>  		};
>  
> +		serdes: phy@1ea0000 {
> +			compatible = "fsl,ls1028a-serdes";
> +			reg = <0x00 0x1ea0000 0x0 0xffff>;

[Severity: Low]
Does this reg property specify a length that is off by one byte?

The reg property size field represents the length of the region in bytes. If
this is a standard 64KB hardware block, should the size be 0x10000 instead
of 0xffff?

Setting the length to 0xffff tracks a memory region that is 1 byte smaller
than the actual block. While ioremap aligns to the page boundary and avoids
runtime side effects, this tracks an incorrect resource length and leaves the
very last byte unmapped by the resource manager.

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#phy-cells = <1>;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630110459.516364-1-ioana.ciornei@nxp.com?part=2

Re: [PATCH 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect 'reg' size property (0xffff instead of 0x10000) for the SerDes blocks, improperly sizing the memory region and missing its last byte.
--

commit e38fd823b92e0ac25dfc572821e4084ac6569201
Author: Vladimir Oltean <vladimir.oltean@nxp.com>

arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks

This patch describes the two Lynx 10G SerDes blocks and their associated lanes
found on the LS1046A SoC. The nodes are initially left disabled at the SoC
level.

> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 6fefe837f434f..db935805c3792 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
>  			clock-names = "sfp";
>  		};
>  
> +		serdes1: phy@1ea0000 {
> +			compatible = "fsl,ls1046a-serdes1";
> +			reg = <0x00 0x1ea0000 0x0 0xffff>;

[Severity: Low]
Is the region size of 0xffff correct here? 

The reg property typically specifies the total size of the block, not the
maximum offset. Should this be 0x10000 to cover the full 64KB block and
include the final byte of the hardware region?

> +			#address-cells = <1>;
> +			#size-cells = <0>;

[ ... ]

> +		serdes2: phy@1eb0000 {
> +			compatible = "fsl,ls1046a-serdes2";
> +			reg = <0x00 0x1eb0000 0x0 0xffff>;

[Severity: Low]
Similarly, does the serdes2 block also need a reg size of 0x10000 instead of
0xffff?

> +			#address-cells = <1>;
> +			#size-cells = <0>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630110459.516364-1-ioana.ciornei@nxp.com?part=3

Re: [PATCH 4/5] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Grammar typo in the commit message.
--

commit 12366d243aefbb596eb3d107281f15d8b29178c8
Author: Vladimir Oltean <vladimir.oltean@nxp.com>

arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks

This commit adds device tree nodes describing the two Lynx 10G SerDes
blocks and their lanes on the LS208xA SoC. The nodes are left disabled
at the SoC level until enabled by board-specific DTs.

> Describe the two Lynx 10G SerDes blocks and their associated lanes found
> on the LS208xA SoC. The nodes are left disabled at the SoC level; board
> DTs will enabled them once there are consumers.

[Severity: Low]
This isn't a bug, but there is a minor grammatical typo here ("enabled"
instead of "enable").

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630110459.516364-1-ioana.ciornei@nxp.com?part=4

Re: [PATCH 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings

[Ioana Ciornei]

On Tue, Jun 30, 2026 at 11:26:25AM +0000, sashiko-bot@kernel.org wrote:

(...)

> [Severity: Medium]
> Did we miss updating the consumer phandles in this patch?
> 
> The commit message indicates consumer phandles need updating to match
> #phy-cells = <0>, but they appear to remain unupdated in the device tree,
> and #phy-cells = <1> is still retained on the parent PHY nodes.
> 

No, the customer phandles don't need to be updated anymore, both modes
are accepted by the driver and dt-binding. Will remove that section from
the commit message.

> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index 1d73abffa6b72..a687eb3e31904 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -621,17 +621,163 @@ soc: soc {
> >  		ranges;
> >  		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> >  
> [ ... ]
> >  		serdes_1: phy@1ea0000 {
> > -			compatible = "fsl,lynx-28g";
> > +			compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
> >  			reg = <0x0 0x1ea0000 0x0 0x1e30>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> >  			#phy-cells = <1>;
> > +			status = "disabled";
> 
> [Severity: High]
> Does this default status = "disabled" unintentionally break interfaces
> wired to serdes_1 on boards like fsl-lx2162a-clearfog and fsl-lx2160a-half-twins?
> 
> These boards consume serdes_1 but do not appear to override the status to
> "okay" in this patch.

Yes, my bad. Will enable serdes_1 on these boards as well.

> 
> [ ... ]
> > +		serdes_3: phy@1ec0000 {
> > +			compatible = "fsl,lx2160a-serdes3";
> > +			reg = <0x0 0x1ec0000 0x0 0x1e30>;
> 
> [Severity: Medium]
> Should serdes_3 include the generic "fsl,lynx-28g" fallback compatible string
> here, similar to what was added for serdes_1 and serdes_2?

No, SerDes block #3 should not use the fallback compatible since it
wasn't supported anyway through the fallback.

> 
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			status = "disabled";
> > +			#phy-cells = <1>;
> [ ... ]
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> > new file mode 100644
> > index 0000000000000..b9629e074d943
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> > @@ -0,0 +1,24 @@
> [ ... ]
> > +&soc {
> > +	/delete-node/ serdes@1ec0000;
> > +};
> 
> [Severity: Low]
> Could this /delete-node/ directive fail at build time?
> 
> In the base fsl-lx2160a.dtsi, the node is defined as phy@1ec0000 rather
> than serdes@1ec0000.

Will fix.

Ioana

Re: [PATCH 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes

[Ioana Ciornei]

On Tue, Jun 30, 2026 at 11:32:28AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The `reg` property for the `serdes` node incorrectly sets the region size to `0xffff` instead of `0x10000`, causing an off-by-one error in the resource length.
> --
> 
> commit a39aeb25ec050b4deb66ed84479cc1400f6ce47b
> Author: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> arm64: dts: ls1028a: describe the Lynx 10G SerDes
> 
> This commit describes the Lynx 10G SerDes block and its 4 SerDes lanes found
> on the LS1028A SoC. The node is left disabled at the SoC level so board
> device trees can enable it once consumer nodes use it.
> 
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> [ ... ]
> > @@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
> >  			};
> >  		};
> >  
> > +		serdes: phy@1ea0000 {
> > +			compatible = "fsl,ls1028a-serdes";
> > +			reg = <0x00 0x1ea0000 0x0 0xffff>;
> 
> [Severity: Low]
> Does this reg property specify a length that is off by one byte?
> 
> The reg property size field represents the length of the region in bytes. If
> this is a standard 64KB hardware block, should the size be 0x10000 instead
> of 0xffff?

The size=0x10000 would "fill" the area until the next SerDes block
starts but the size of the SerDes block as described in the RM is even
smaller - 8KB. I will change it to 0x2000.

Ioana

Re: [PATCH 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs

[Frank Li]

On Tue, Jun 30, 2026 at 02:04:54PM +0300, Ioana Ciornei wrote:
> This patch set adds the device tree nodes for the Lynx10G SerDes blocks
> found on the LS1028A, LS1046A, LS1088A and LS2088A SoCs.
>
> The first patch also transitions the LX2160A SoC dtsi to use the
> device-specific Lynx28G SerDes compatible.
>

Next time please cc imx@lists.linux.dev, otherwise, patchwork can't see
this patch.

I sent patch to update maintainers file

https://lore.kernel.org/imx/20260630201618.3497941-1-Frank.Li@oss.nxp.com/#R

Frank

> Ioana Ciornei (1):
>   arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
>
> Vladimir Oltean (4):
>   arm64: dts: lx2160a: transition to device-specific SerDes compatible
>     strings
>   arm64: dts: ls1028a: describe the Lynx 10G SerDes
>   arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
>   arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
>
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  29 ++++
>  .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  60 +++++++
>  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  58 +++++++
>  .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  98 ++++++++++++
>  .../freescale/fsl-lx2160a-clearfog-itx.dtsi   |   4 +
>  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |   4 +
>  .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
>  .../dts/freescale/fsl-lx2162a-clearfog.dts    |   2 +-
>  .../boot/dts/freescale/fsl-lx2162a-qds.dts    |   2 +-
>  .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi |  24 +++
>  10 files changed, 427 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
>
> --
> 2.25.1
>

Re: [PATCH 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs

[Ioana Ciornei]

On Tue, Jun 30, 2026 at 04:20:54PM -0400, Frank Li wrote:
> On Tue, Jun 30, 2026 at 02:04:54PM +0300, Ioana Ciornei wrote:
> > This patch set adds the device tree nodes for the Lynx10G SerDes blocks
> > found on the LS1028A, LS1046A, LS1088A and LS2088A SoCs.
> >
> > The first patch also transitions the LX2160A SoC dtsi to use the
> > device-specific Lynx28G SerDes compatible.
> >
> 
> Next time please cc imx@lists.linux.dev, otherwise, patchwork can't see
> this patch.

Ok, sure. Will send shortly a v2 integrating some changes generated by
the sashiko review.

Thanks!